Fujitsu Series 3 Manual

 
3. USB host operations 
 
  A device connection is detected. 
Figure 3-13 Resume operation by device connection (Full-speed mode) 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
Connection
Host pin D
 +
Host pin D
 - 
CNNIRQ bit of HIRQ 
 
 
RWKIRQ bit of HIRQ 
(RWKIRE =1 )
(
CNNIRE
 = )
1
An interrupt 
. 
occurs
CSTAT bit of HSTATE
2.5 s or more
:  Drive by pul l- up or pull - down resistor
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E 
1155 
MB9Axxx/MB9Bxxx  Series  

 
3. USB host operations 
 
3.11. Device disconnection 
The device disconnection timer starts when both the host pins D+ and D- are set to LOW. If 
LOW is detected for 2.5s or more, the CSTAT  bit of the Host S
 tatus Register (HSTATE) is 
set to 0. 
  Device disconnection 
If both the host pins D+ and D- remain set to LOW for 2.5 s or more regardless of the host or function 
mode, it is judged that the device has been disconnected. This then sets 0 to the CSTAT bit of the Host 
Status Register...

 
4. USB host setting procedure examples 
 
4.  USB host setting procedure examples 
The following shows the flowchart for each token in the USB host. 
 Initialization and device detection  
Start
UDCC.RST=1
HCNT0.HOST=1 // Host mode setting
EP1C setting
EP2C setting
HIRQ.CNNIRQ=1?No
// Device connection
Yes
HSTATE.TMODE=1?No
Yes
HSTATE.CLKSEL=1
// Low-speed detection
// Full-speed detection
HSTATE.CLKSEL = 
Setting value?No
Yes
// Bus resetting
HIRQ.URIRQ=1? No
Yes
HIRQ.CNNIRQ=1? No
Yes...

 
4. USB host setting procedure examples 
 
 IN, OUT, or SETUP token 
 
EP1S.BFINI=0
EP2S.BFINI=0
IN token
HADR setting
EP1C setting
EP2C setting
// Select the transfer direction and specify the packet size. (*)
// Select the transfer direction and specify the packet size. (*)
HTOKEN setting// Toggle, endpoint, or IN setting
HIRQ.CMPIRQ=1?No
Yes
HERR.LSTSOF=1?Yes
No
HERR.TOUT=1?Yes
No
HERR.TGERR=1?Yes
No
HERR.HS=00?No
Yes
Error 
processing
Read the received data. (EPnDT)
EPnS.DRQ=0
EP1S.BFINI=1...

 
4. USB host setting procedure examples 
 
  
EP1S.BFINI=0
EP2S.BFINI=0
OUT token
HADR setting
EP1C setting
EP2C setting
// Select the transfer direction and specify the packet size.
// Select the transfer direction  and specify the packet size.
HTOKEN setting
// Toggle, endpoint, or OUT setting
HIRQ.CMPIRQ=1?No
Yes
HERR.LSTSOF=1?Yes
No
HERR.TOUT=1?Yes
No
HERR.HS=00?No
Yes
Error 
processing
EPnS.DRQ=0
EP1S.BFINI=1
EP2S.BFINI=1
End
Write the send data. (EPnDT)// n=1 or 2
// n=1 or 2
Enumeration?
No
Yes//...

 
4. USB host setting procedure examples 
 
  
EP1S.BFINI=0
EP2S.BFINI=0
SETUP token
HADR setting
EP1C setting
EP2C setting
// Select the transfer direction and specify the packet size.
// Select the transfer direction and specify the packet size.
HTOKEN setting// Toggle, endpoint, or OUT setting
HIRQ.CMPIRQ=1?No
Yes
HERR.LSTSOF=1?Yes
No
HERR.TOUT=1?Yes
No
HERR.HS=00?No
Yes
Error 
processing
EPnS.DRQ=0
EP1S.BFINI=1
EP2S.BFINI=1
End
Write setup data. (EPnDT)// n=1 or 2
// n=1 or 2
Enumeration?
No
Yes//...

 
4. USB host setting procedure examples 
 
 SOF token 
 
HFRAME setting
HEOF setting
HTOKEN setting// SOF setting (TGGL and ENDPT ignored)
HIRQ.CMPIRQ=1?No
Yes
HERR.LSTSOF=1?Yes
No
End
Error 
processing
SOF token
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E 
1161 
MB9Axxx/MB9Bxxx  Series  

 
5. USB host registers 
 
5.  USB host registers 
This section explains the configuration and functions of the registers used for the USB host. 
 List of USB host registers 
Abbreviation Register  name See 
UDCC UDC Control Register  * 
EP1C EP1 Control Register  * 
EP2C EP2 Control Register  * 
EP1S EP1 Status Register  * 
EP2S EP2 Status Register  * 
EP1DTH EP0 Data Register high-order  * 
EP1DTL EP0 Data Register low-order  * 
EP2DTH EP0 Data Register high-order  * 
EP2DTL EP0 Data Register...

 
5. USB host registers 
 
 UDCC.RST dependent register  bit update timing list 
 Register  Bit 
FUJITSU SEMICONDUCTOR LIMITED 
HCNT0 HOST 
HSTATE CLKSEL 
Register bits to be updated when 
UDCC.RST=1 
EP1C EPEN, TYPE, DIR, PKS1 
EP2C EPEN,  TYPE, DIR, PK

S2 
HCNT0 URST 
HIRQ TCAN, RWKIRQ, URIRQ, CMPIRQ, 
CNNIRQ, DIRQ, SOFIRQ 
Register bits initialized when 
UDCC.RST=1 
(Update when UDCC.RST=0) 
HERR 
(All bits)  LSTSOF, RERR, 
T
 OUT, CRC, TGERR, 
STUFF, HS 
HSTATE SOFBUSY, SUSP 
HFRAME FRAME0, FRAME1...

 
5. USB host registers 
 
5.1.  Host Control Registers 0 and 1 (HCNT0 and HCNT1) 
Host Control Registers 0 and 1 (HCNT0 and HCNT1) are used to specify the USB operation 
mode and interrupt. 
 Host Control Register 1 (HCNT1)   
bit  15 14 13  12 11 10  9 8 
Field Reserved Reserved Reserved ReservedReservedSOFSTEP  CANCEL  RETRY
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 1 
Reset enabled    or not*  x x x 
x x x x x 
* : Enables or disables a reset with the  RST bit of...