Fujitsu Series 3 Manual

 
5. USB host registers 
 
[bit 9] CANCEL (token CANCEL enable) 
This is s token cancellation enable bit. 
When 1 is set to this bit, if the target token is written to the Host Token Endpoint Register (HTOKEN) in 
the EOF area (specified in the EOF Se tting Register), its sending is canceled. When 0 is set to this bit, 
token sending is not canceled even if the target toke n is written to the register. The cancellation of token 
sending is detected by reading the TCAN bit of the Host Interrupt Register...

 
5. USB host registers 
 
[bit 7] RWKIRE (Remove WaKe up Interrupt Request Enable) 
This is a resume interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if the RWKIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the RWIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt after restarting. 
1  Enables an interrupt after restarting. 
 
 
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it is not...

 
5. USB host registers 
 
[bit 4] CNNIRE (CoNNection Interrupt Request Enable) 
This is a device connection detection interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if the CNNIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the CNNIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt at device connection. 
1 Enables an interrupt at device connection....

 
5. USB host registers 
 
[bit 1] URST (Usb bus ReSeT) 
This is a bus reset bit. 
When 1 is set to this bit, the USB bus is reset. This bit continues set to 1 during USB bus resetting, and 
changes to 0 when USB bus resetting is ended. If 0  is set to this bit, no processing is performed. 
Bit Description 
0 Holds the status of the USB bus. 
1 Resets the USB bus. 
 
 
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 No processing is performed even if this bit is set to 1 while the RST bit of the UDC Control Register 
(UDCC) is 1. 

 This bit...

 
5. USB host registers 
 
5.2.  Host Interrupt Register (HIRQ) 
The Host Interrupt Register (HIRQ) indicates the USB host interrupt request flag. A host 
interrupt can occur by setting the interrupt enable bit of the Host Cont\
rol Register (HCNT0 or 
HCNT1), excluding the TCAN bit. 
 bit 7 6 5 4 3 2 1 0 
Field TCAN Reserved RWKIRQUR IRQCMPIRQCNNIRQ DIRQ SOFIRQ
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Reset enabled    or not*  x x 
                  
* : Enables or...

 
5. USB host registers 
 
[bit 5] RWKIRQ (Remove WaKe up Interrupt ReQuest) 
This is a remote Wake-up end flag. 
If this bit is set to 1, it means that remote Wake-up is ended. When this bit is 0, it has no meaning. If this 
bit is written with 0, it is set to 0. However, if this bit is written with 1, its value is ignored. 
When the RWKIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs if this bit is set to 
1. 
Bit Description 
0  Issues no interrupt request by restart. 
1 Issues an...

 
5. USB host registers 
 
[bit 3] CMPIRQ (CoMPletion Interrupt ReQuest) 
This is a token completion flag. 
If this bit is set to 1, it means that a token is completed. When this bit is 0, it has no meaning. If this bit 
is written with 0, it is set to 0. However, if  this bit is written with 1, its value is ignored. 
When the CMPIRE bit of Host Control Register 0 (HCNT0)  is 1, an interrupt occurs if this bit is set to 
1. 
Bit Description 
0  Issues no interrupt request by token completion. 
1 Issues...

 
5. USB host registers 
 
[bit 1] DIRQ (Disconnection Interrupt ReQuest) 
This is a device disconnection detection flag. 
If this bit is set to 1, it means that a device disconnection is detected. When this bit is 0, it has no 
meaning. If this bit is written with 0, it is set to 0. However, if this bit is written with 1, its value is 
ignored. 
When the DIRE bit of Host Control Register 0 (HCNT0) is  1, an interrupt occurs if this bit is set to 1. 
Bit Description 
0 Issues no interrupt request by...

 
5. USB host registers 
 
5.3.  Host Error Status Register (HERR) 
The Host Error Status Register (HERR) indicates whether or not an error occurs while 
sending or receiving data in the host mode. 
 bit 15 14 13 12 11 10 9 8 
Field LSTSOFRERR TOUT CRC TGERRSTUFFHS 
Attribute  R/W R/W R/W  R/W R/W R/W  R/W 
Initial value 0 0 0  0 0 0  11 
Reset enabled or  not*   
                   
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 15] LSTSOF (LoST...

 
5. USB host registers 
 
[bit 13] TOUT (Time OUT) 
This is a timeout flag. 
If this bit is set to 1, it means that no response is returned from the device within the specified time after a 
token has been sent in the host mode. When this bit is 0, it means that no timeout is detected. When this 
bit is 0, it means that no error occurs. If this bit is written with 0, it is set to 0. However, if this bit is 
written with 1, its value is ignored. 
Bit Description 
0 No timeout 
1 Timeout occurs. 
 
 
This...