Fujitsu Series 3 Manual

 
1. Overview of USB host 
 
Chapter: USB Host 
This chapter explains the functions and operations of the USB host. 
 
1.
   Overview of USB host
2.
   USB host configuration
3.
   USB host operations
4.
   USB host setting procedure examples
5.
   USB host registers
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FW03H
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E18.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E 
1135 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview of USB host 
 
1.  Overview of USB host 
This section explains the functions and operations of the USB host. 
 Features of USB host 
The USB host has the following features: 
  Automatic detection of full-speed or low-speed transfer 
   Support of full-speed or low-speed transfer 
   Automatic detection of device connection or disconnection 
   Support of USB bus reset sending function 
   Support of IN, OUT, SETUP, and SOF tokens 
   Automatic sending of handshake packet for IN...

 
1. Overview of USB host 
 
Table 1-1 Restrictions in USB host specifications  Host 
o*1 
Hub support 
FUJITSU SEMICONDUCTOR LIMITED 
Bulk transfer  o Transfer functions 
Control transfer  o 
Interrupt transfer o 
Isochronous t

ransfer  o 
Low Speed  o Transfer speed modes 
Full Speed o 
PRE packet support  x 
SOF packet support o 
CRC error o Error types 
Toggle error  o 
Timeout o 
Max. packet < Received data  o 
Detection of device connection or disconnection  o 
Detection of transfer speed  o 
o:...

 
2. USB host configuration 
 
2.  USB host configuration 
Figure 2-1 shows the USB host block diagram. 
 USB host block diagram 
Figure 2-1 USB host block diagram 
 
On-chip bus
UDP
UDM
UDC
CPU interface
UDCC
HCNT0,1 HIRQ
HERR
HSTATE
HFCOMP
HRTIMER HADRHEOF
HFRAME HTOKEN
UDC 
interface
USB clock (48 MHz)
From USB clock 
generation unit
I/O
Interrupt
Interrupt
SUSP
Endpoint 1  buffer
Endpoint 2 
buffer
Host 
control unit
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E...

 
3. USB host operations 
 
3.  USB host operations 
This section explains the operations of the USB host. 
 
3.1 Device connection  
3.2  USB bus resetting  
3.3  Token packet  
3.4  Data packet  
3.5  Handshake packet  
3.6  Retry function  
3.7  SOF interrupt  
3.8  Error status  
3.9  End of packet  
3.10  Suspend and resume operations  
3.11  Device disconnection 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E 
1139 
MB9Axxx/MB9Bxxx  Series  

 
3. USB host operations 
 
3.1. Device connection 
This section shows how to detect that an external USB device is connected using software. 
 Host function setting 
To carry out USB operation, configure the setting of the USB clock generation unit and enable the USB 
clock output while the USBEN bit of the USB Enable  Register (USBEN) is 0 (USB operation disabled). 
Next, set the USBEN bit to 1 (USB operation enabled).  Then, to operate the USB as a host, set 1 to the 
HOST bit of Host Control...

 
3. USB host operations 
 
Figure 3-1 Full-speed device connection detection timing example (HCNT0 bit 0=0) 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
Device 
connection
Host pin D
 + 
Host pin D - 
2.5  s or more
CSTAT bit of HSTATE
Undefined
TMO D
 E bi

t of HSTATE
CNNIRQ bit of HIRQ
 
 0 
 
HOST bit of HCNT
 
 
  When 2. 5

s laps ed
  after an external USB device was co nnected, the CSTAT bit of the Host Status 
Register (HSTATE) is changed to 1. 
   The TMODE and CSTAT bits of the Host Status Regi...

 
3. USB host operations 
 
3.2.  USB bus resetting 
The USB bus is reset by sending SE0 for 10 ms or more if the URST bit of Host Control 
Register 0 (HCNT0) is set to 1 in the host mode. After USB bus resetting has been 
completed, the URST bit of Host Control Register 0 (HCNT0) is set to 0, and the URIRQ bit 
of the Host Interrupt Register (HIRQ) is set to 1
. If the URIRE bit of Host Control Register 0 
(HCNT0) is then set to 1, an interrupt occurs. To clear this interrupt, write 0 to the URIRQ 
bit...

 
3. USB host operations 
 
3.3. Token packet 
When issuing an IN, OUT, or SETUP token in the host mode, use the following setting steps to 
send a token packet. 
1.  Set the Host Address Register (HADR). 
2.  Set the DIR and PKS bits of the E
P1 Control Register (EP1C) or EP2 Control Register 
(EP2C). 
3.  Write the required data to the Host Token Endpoint Register (HTOKEN). 
When issuing an SOF token, set the Frame  Setup Register (HFRAME) and EOF Setup 
Register (HEOF), and write the required data to...

 
3. USB host operations 
 
Figure 3-3 Example of register setting to issue an IN, OUT, or SETUP token 
 
Write to HADR
(if a change is required)Write to EP1C or EP2C.
(if a change is required)
Write to HTOKEN.
Register write signal
Check the status of the endpoint 1 or 2 buffer.
  
 
When issuing an SOF token, specify the EOF time  in the EOF Setup Register (HEOF) and the frame 
number in the Frame Setup Register (HFRAME) respectively. Then specify an SOF token code in the 
TKNEN bit of the Host Token...