Fujitsu Series 3 Manual

 
5. USB host registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB Host 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  52 
[bit 6:4] TKNEN (ToKeN ENable) 
These are token enable bits. 
These bits send a token according to the settings. Afte r operation has been ended, the TKNEN bit is set to 
000, and the CMPIRQ bit of the Host Interrupt Register  (HIRQ) is set to 1. If the CMPIRE bit of Host 
Control Register 0 (HCNT0) is 1, an interrupt occurs. 
The settings of the TGGL and ENDPT bits  are ignored when...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
1186 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview and configuration 
 
Chapter: CAN Prescaler 
This chapter describes the CAN prescaler. 
 
1. Overview and configuration 
2. CAN Prescaler Register 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CODE: 9BFCANPRE-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-1: CAN Prescaler 
MN706-00002-1v0-E 
1187 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview and configuration 
 
1.  Overview and configuration 
The CAN prescaler generates a CAN system clock (fsys) and supplies it to the CAN. 
The CAN prescaler divides a CAN prescaler clock by 1 to 12 frequency, and supplies it to the CAN as a 
CAN system clock (fsys). 
Figure 1-1  shows the block diagram of the CAN prescaler. 
 CAN block diagram 
Figure 1-1 Generating a CAN system clock (fsys) 
PLL oscillation enable (SCM_CTL.PLLE)
Standby
STOP mode
TIMER mode
Sub clock mode
Low-speed CR mode...

 
2. CAN Prescaler Register 
 
2.  CAN Prescaler Register 
This chapter describes the CAN Prescaler Register. 
Abbreviation Register name See 
CANPRE CAN Prescaler Register  2.1 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-1: CAN Prescaler 
MN706-00002-1v0-E 
1189 
MB9Axxx/MB9Bxxx  Series  

 
2. CAN Prescaler Register 
 
2.1.  CAN Prescaler Register (CANPRE) 
The CAN Prescaler Register is used to configure the CAN system clock (fsys) generation 
prescaler. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved Reserved  CANPRE 
Attribute R/W0 - -  - R/W R/W  R/W R/W 
Initial value 0 0 0  0 1 0 1 1 
 
  Register functions 
[Bit7] Reserved bit 
Be sure to write 0. 
[Bit6:4] Reserved bits  Logical 0 is always read. In the write mode, set 0. 
[Bit3:0] CANPRE:    CAN prescaler setting...

 
2. CAN Prescaler Register 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: CAN Prescaler 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  6 
 
   Before changing the value of the CAN prescaler setting bit, set the initialization bit of the CAN Control 
Register (CTRLR) to 1, and stop all bus operations. 
   To use the PLL output as a CAN prescaler clock, se t the initialization bit of the CAN Control Register 
(CTRLR) to 0 after PLL oscillation has been stabilized. 
   Make sure that the CAN system clock output  by...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
1192 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
CHAPTER: CAN Controller 
This chapter explains CAN. 
 1.
 Overview 
2. Configuration 
3. CAN Controller Operations 
4. CAN Registers  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FC42-E02.1 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1193 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
The CAN controller complies with CAN protocol version 2.0A/B, a standard protocol for serial 
communication.CAN is widely used in various industrial fields such as automobile and factory 
automation. 
The CAN controller has the following features: 
  Supports CAN protocol version 2.0A/B 
   Supports a bit rate up to 1 Mbits/s 
   Identifier mask for each message object 
   Supports programmable FIFO mode 
   Maskable interrupt 
   Supports 32 message buffers 
...