Fujitsu Series 3 Manual

 
4. CAN Registers 
 
[bit 4] RxOk: Successful message reception bit 
Bit Function 
0 No message has been transferred successfully on the CAN bus, or the bus is in 
idle state.    [Initial value] 
1 
A messages has been transferred successfully on the CAN bus. 
 
[bit 3] TxOk: Successful message transmission bit 
Bit Function 
0  The bus is in idle state, or no message has been sent successfully.    [Initial value] 
1  A messages has been sent successfully. 
 
 
The R x

Ok and TxOk bits can be reset...

 
4. CAN Registers 
 
   If the BOff and EWarn bits change while the EIE bit is  1, or if th
 e RxOk, TxOk, and LEC bits change 
while the SIE bit is 1, the status interrupt code  (0x8000) is written to the CAN Interrupt Register. 
   Writing from the CPU updates the RxOk and TxOk bits, and this erases the RxOk and TxOk bits set by 
the CAN controller. If the RxOk and TxOk bits are used, clear the RxOk and TxOk bits within the time 
(45 x BT) after they are set to 1. BT indicates one bit time. 
   If...

 
4. CAN Registers 
 
4.2.3. CAN Error Counter (ERRCNT) 
The CAN Error Counter indicates the receive error passive, the receive error counter, and the 
send error counter. 
 Register configuration 
- CAN Error Counter (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field RP REC6-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Error Counter (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field TEC7-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial...

 
4. CAN Registers 
 
[bit 7:0] TEC7-0: Send error counter A send error counter value. The range of the send error counter value is between 0 and 255. 
If the send error counter reaches or  exceeds 256, the Init bit of the CAN Control Register is set to 1, and 
the counter is not refreshed. 
Example:  If a send error adds 8 to TEC7-0 = 255 with Init = 0,   
    then TEC7-0 = 255 with Init = 1. 
  If a send error adds 8 to TEC7-0 = 254 with Init = 0,   
    then TEC7-0 = 254 with Init = 1.   
  If a...

 
4. CAN Registers 
 
4.2.4. CAN Bit Timing Register (BTR) 
The CAN Bit Timing Register configures the prescaler and the bit timing. 
 Register configuration 
- CAN Bit Timing Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedTSeg2 TSeg1 
Attribute  R0,W0 R/W R/W  R/W R/W R/W  R/W R/W 
Initial value 0 0 1  0 0 0 1 1 
 
- CAN Bit Timing Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field SJW  BRP 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 1 
 
...

 
4. CAN Registers 
 
4.2.5. CAN Interrupt Register (INTR) 
The CAN Interrupt Register indicates message interrupt code and status interrupt code. 
 Register configuration 
- CAN Interrupt Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field IntId15-8 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Interrupt Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field IntId7-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0...

 
4. CAN Registers 
 
4.2.6. CAN Test Register (TESTR) 
The CAN Test Register is used to monitor the setting of test mode and RX pin. For\
 operations, 
see 3.7 Test mode. 
  Register configuration 
- CAN Test Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Test Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Rx  Tx1...

 
4. CAN Registers 
 
[bit 3] Silent: Silent mode 
Bit Function 
0 Disables silent mode.    [Initial value] 
1 Enables silent mode. 
 
[bit 2] Basic: Basic mode 
Bit Function 
0  Disables basic mode. [Initial value] 
1 Enables basic mode. 
The IF1 register is used for a sent me
ssage, and the IF2 register for a received 
message. 
 
[bit 1:0] Reserved bits  Reserved bits are read as 0, an d must be set to 0 when writing. 
 
    After setting 1  to th

e Te
 st bit of the CAN Control Regi ster, write...

 
4. CAN Registers 
 
4.2.7. CAN Prescaler Extension Register (BRPER) 
The CAN Prescaler Extension Register is used to extend the prescaler used in the CAN 
controller by combining it with the prescaler specified at a CAN bit timing. 
 Register configuration 
- CAN Prescaler Extension Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0...

 
4. CAN Registers 
 
4.3.  Message interface registers 
The CAN controller provides two message interface registers to control an access from the 
CPU to the message RAM. 
The CAN controller provides two message interface registers to control an access from the CPU to the 
message RAM. These two registers are used to avoi d a confliction between an access from the CPU to the 
message RAM and an access from the CAN controller to  the message RAM by buffering the data (message 
object) transferred or to...