Fujitsu Series 3 Manual

 
4. CAN Registers 
 
4.3.6. IFx Data Registers A1, A2, B1, and B2 (IFxDTA1, IFxDTA2, IFxDTB1, and IFxDTB2) 
The IFx Data Registers A1, A2, B1, and B2 are used to write or read message object sending 
or receiving data to or from the message RAM. Those registers are used only to send or 
receive a data frame, and not to send or receive a remote frame. 
 Register configuration 
  addr+3 addr+2 addr+1 addr+0 
IFx Data A Register 1 (Little endian)    Data(1)  Data(0) 
IFx Data A Register 2 (Little endian)...

 
4. CAN Registers 
 
4.4. Message objects 
The message RAM provides 32 message objects. To avoid a confliction when simultaneously 
accessing the message RAM from the CPU and the CAN controller, the CPU cannot directly 
access message objects. The message RAM is accessed via the IFx Message Interface 
Register. 
This section explains the configuration and functions of a message object. 
 Configuration of message object 
NewDatUMask
MsgVal
Msk28-0
ID28-0
MXtd
Xtd
MDir
Dir
EoB
DLC3-0Data0Data1
MsgLst...

 
4. CAN Registers 
 
   Reset the MsgVal bit of an unused m
 essage object to 0 before clearing the Init bit of the CAN Control 
Register to 0. 
   Be sure to reset the MsgVal bit of a message object  to 0 before changing the value of ID28-0, Xtd, Dir, 
or DLC3-0. 
   If the MsgVal bit of a message object is cleared to  0 during transmission, the TxOk bit of the CAN 
Status Register is set to 1 when transmission has been completed. However, the TxRqst bits of the 
message object and CAN Transmit...

 
4. CAN Registers 
 
MXtd : Extension ID mask bit 
Bit Function 
0 Does not compare the set value of the Xtd bit in a message object with that of the 
IDE bit of a received frame. Determine whet
her to perform the comparison as the 
ID of a standard frame or extension frame based on the IDE bit of a received 
frame. 
1  Compares the set value of the Xtd bit in a message object with that of the IDE bit 
of a received frame. 
 
 
When  a 

11-bit ID (standard frame) is set to a message  object, the ID of...

 
4. CAN Registers 
 
EoB: End of buffer bit (For details, see 3.4 FIFO buffer function .) 
Bit Function 
0 Indicates that a message object is used as a FIFO buffer, not the last message. 
1 Indicates a single message object or the  last message object in the FIFO buffer. 
 
 
  The Eo B 

bit is used to configure a FIFO  buff
 er for message objects 2 to 32. 
   When processing a single message object without using a FIFO buffer, be sure to set the EoB bit to 1. 
 
NewDat: Data update bit 
Bit...

 
4. CAN Registers 
 
IntPnd: Interrupt pending bit 
Bit Function 
0 No interrupt cause is detected. 
1 An interrupt cause is detected. 
If other high-priority interrupt is not found, the IntId bit of the CAN Interrupt 
Register indicates this message object. 
 
RmtEn: Remote enable 
Bit Function 
0  Does not change the value of the TxRqst bit when a remote frame has been received. 
1 Sets the TxRqst bit to 1 when a remote frame is received while the Dir bit is 1. 
 
 
When  t

he Dir bit is 1 and the...

 
4. CAN Registers 
 
Data 0-7: Data 0 to 7 
 Function 
Data 0 First data byte in CAN data frame 
Data 1  2nd data byte in CAN data frame 
Data 2 3rd data byte in CAN data frame 
Data 3 4th data byte in CAN data frame 
Data 4 5th data byte in CAN data frame 
Data 5 6th data byte in CAN data frame 
Data 6 7th data byte in CAN data frame 
Data 7 8th data byte in CAN data frame 
 
 
  Serial da ta is ou

tput from the MSB (bit 7 or bit 15) to the CAN bus. 
   If the receive d 

message data is lower than...

 
4. CAN Registers 
 
4.5.  Message handler registers 
Message handler registers are all in read only mode. The TxRqst, NewDat, IntPnd, and 
MsgVal bits of a message object and the IntId bit indicate the status. 
 Message handler registers 
  CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) 
   CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) 
   CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) 
   CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER...

 
4. CAN Registers 
 
4.5.1. CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) 
The CAN Transmit Request Register indicates the TxRqst bit of all message objects. This 
register checks which message object transmission request is pending by reading the TxRqst 
bit. 
 Register configuration 
- CAN Transmit Request Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field TxRqst32-25 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Transmit Request...

 
4. CAN Registers 
 
  Resetting conditions 
   Set 1 to the WR/RD bit of the IFx Command Mask Register, 0 to the TxRqst bit, and 1 to the 
Control, and 0 to the TxRqst bit of the IFx Message Control Register. Then write data to the IFx 
Command Request Register to reset the TxRqst bit of a specific message object. 
   The TxRqst bit is reset when frame  transmission has finished successfully. 
   If the Dir bit is 1, the RmtEN bit is 0, and th e UMask bit is 1, the TxRqst bit is reset by 
receiving...