Fujitsu Series 3 Manual

 
3. CRC Registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
Chapter: CRC (Cyclic Redundancy Check) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  16 
3.4. CRC Register (CRCR) 
The CRC Register (CRCR) is used to output the  CRC calculation result. This register must be 
initialized before start calculating. 
 
bit 31       0 
Field D31-D0 
Attribute R 
Initial value  0xFFFFFFFF 
 
[bit 31:0] D31 to D0: CRC bit  This bit is used to read the CRC calculation result.  If 1 is written to the initialization bit (CRCCR.INIT),...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
1276 
MB9Axxx/MB9Bxxx  Series  

 
1. External Bus Interface Features 
 
Chapter: External Bus Interface 
This chapter explains the functions and operations of the external bus interface. 
 
1.
 External Bus Interface Features 
2. Block Diagram 
3. Operation 
4. Example waveforms of external memory access 
5. Endianness and Valid Byte Lanes 
6. Connection Examples 
7. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFEXTBUS-E01.1_MEMCS-E1.5 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  23: External  Bus Interface...

 
1. External Bus Interface Features 
 
1.  External Bus Interface Features 
This section explains features of the external bus interface. 
 External bus interface features 
  Supports 8-bit/16-bit wide SRAM/flash memories. 
   Provides eight chip select ar eas for an SRAM/flash memory. 
   Can configure parameters individually for each chip select area for an SRAM/flash memory. 
   Can access the device during NAND flash memory access.  (Exclusive access control is not required.) 
   Supports NOR...

 
2. Block Diagram 
 
2. Block Diagram 
This section explains the block diagram of the external bus interface. 
Figure 2-1 External bus interface block diagram 
 
This LSI
Control block
External bus interface
AHB interface
Register block
AHB bus
APB bus
External memory bus
I/O
  
  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  23: External  Bus Interface 
MN706-00002-1v0-E 
1279 
MB9Axxx/MB9Bxxx  Series  

 
3. Operation 
 
3. Operation 
The section explains the operations of the external bus interface. 
The external bus interface can connect with SRAM and flash memories. 
The external bus interface has eight chip select signals. 
 
3.1 Fundamental SRAM and  flash memo
ry accesses 
3.

2   NAND flash memory access 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  23: External  Bus Interface 
MN706-00002-1v0-E 
1280 
MB9Axxx/MB9Bxxx  Series  

 
3. Operation 
 
3.1.  Fundamental SRAM and flash memory accesses 
The following explains fundamental SRAM and flash memory accesses. 
The external bus interface has a 256 MB address space. Each address can be configured without restrictions. 
(The actual maximum address size is 32 MB if the external output address width is taken into 
consideration.) 
A different timing can be specified for each chip se lect signal. NAND and NOR flash memories can be 
connected. The NOR flash memory can be accessed as...

 
3. Operation 
 
3.2.  NAND flash memory access 
The following explains NAND flash memory access. 
An access to a NAND flash memory requires different processes from usual SRAM accesses. 
A NAND flash memory has a (512+16) byte internal  register (an 8-bit/16-bit NAND flash memory has a 
(1024+32) byte register). 
Those registers are used to set the basic  data access. For the read operation, several  s to up to several tens 
of  s is required until data is loaded into the internal  register. For the...

 
3. Operation 
 
3.2.1.   Read access to NAND flash memory 
Figure 3-1 shows the flowchart of read access to NAND flash memory. 
Figure 3-1 Flowchart of read access to NAND flash memory. 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
End read access
Turn NAND mode ON 
Single page data read  (Base+0x0000) 
Status read   (Base+0x0000) 
Y 
Sta t us  = O K ?N
Issue a read command 0x00   (Base+0x1000) 
Issue a status read command 0x70   (Base+0x1000)
 Issue an address   (Base+0x2000) 
Issue a read command 0x00 
...

 
3. Operation 
 
3.2.2. Write (auto program) access 
Figure 3-2 shows the flowchart of the write (auto program) access. 
Figure 3-2 Write (auto program) access flowchart 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
Issue a status read command 0x70  (Base+0x1000)
Issue a page program command 0x10   (Base+0x1000)
Status read   (Base+0x0000) 
Y 
Sta t us  O K ? = N
End write (Auto Program) 
  Issue a write command 0x80 
 (Base+0x1000)
Issue an address   (Base+0x2000) 
 
Clear MNALE (optional value)  ...