Fujitsu Series 3 Manual

 
7. Registers 
 
 
 If you write a disabled value to a WWEC, WADC or WA CC bit, operation of the external bus interface is 
not guaranteed. 

 In NAND flash memory mode, the MNWEX and MNREX timings are set by the timing registers as is 
the case with MWEX and MOEX. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  23: External  Bus Interface 
MN706-00002-1v0-E 
1305 
MB9Axxx/MB9Bxxx  Series  

 
7. Registers 
 
7.3.  Area Register 0 to Area Register 7 
The following shows the configuration of the Area Register (0 to 7). 
 
bit 31 30 29 28 27 2625242322212019 18 17 16
Field Reserved MASK 
Attribute -  R/W 
Initial 
value  - 001111 (16MB width) 
                   
bit  15 14  13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field Reserved  ADDR 
Attribute -  R/W 
Initial 
value  -  (from MCSX[0])
 
00000000, 00010000, 00100000,   
00110000, 01000000, 01010000,    01100000, 01110000 
*1 
 
[bit 22:16] MASK:...

 
7. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: External Bus Interface 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  32 
[bit  7:0] ADDR: Address 
These bits specify the address to  set the corresponding MCSX area. 
The address is in the fixed 256 MB area assigned to the SRAM/flash memory interface. 
The address specified by bits 7:0 corresponds to the internal address [27:20]. 
 
No address areas must overlap other areas. 
If unused MCSX is accessed, operation of the exte rnal bus interface is also not...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
1308 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
Chapter: Debug Interface 
This chapter explains the function and operation of the debug interface. 
 
1.
 Overview 
2. Pin Description 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFDEBUG-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  24: Debug  Interface 
MN706-00002-1v0-E 
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MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
This series contains a Serial Wire JTAG Debug Port (SWJ-DP). 
Connecting an ICE to the SWJ-DP allows system debugging. 
This series also contains an Embed

ded Trace Macro Cell (ETM) for tracing instructions and a 
Trace Port Interface Unit (TPIU) that controls trace data. 
This section describes the functions of the pins to be used for debugging. 
For details on the SWJ-DP, ETM, TPIU and system  debug, see Cortex-M3 Technical Reference Manual. 
 Features 
Five pins are...

 
2. Pin Description 
 
2. Pin Description 
This section describes pins. 
 
2.1 Pins for Debug Purposes  
2.2  ETM Pins  
2.3  Functions Initially Assigned to Pins  
2.4  Internal Pull-Ups of JTAG Pins 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  24: Debug  Interface 
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MB9Axxx/MB9Bxxx  Series  

 
2. Pin Description 
 
2.1.  Pins for Debug Purposes 
Five pins (TRSTX, TCK, TMS, TDI, and TDO) are assigned to the JTAG and two pins 
(SWCLK and SWDIO) are assigned to the serial wire. In addition, a Serial Wire Viewer signal 
(SWO) that outputs trace data is assigned. 
TMS is shared with SWDIO, TCK is shared with SWCLK, and TDO is shared with SWO. 
The following provides a list of pin functions in each debug mode. 
Table 2-1 SWJ-DP pin functions in debug mode Pin JTAG  Serial Wire/Trace 
TCK/SWCLK...

 
2. Pin Description 
 
2.2. ETM Pins 
The ETM is assigned four trace outputs (TRACED0, TRACED1, TRACED2, and TRACED3) 
and one clock (TRACECLK). 
The following provides a list of pin functions in each debug mode. 
Table 2-2 Trace pin functions in debug mode Pin Trace 
TRACED0 Synchronous  Trace Data Output signal 
TRACED1 Synchronous  Trace Data Output signal 
TRACED2 Synchronous  Trace Data Output signal 
TRACED3 Synchronous  Trace Data Output signal 
TRACECLK  Trace Clock signal 
 
FUJITSU...

 
2. Pin Description 
 
2.3.  Functions Initially Assigned to Pins 
The 10 pins - five JTAG pins and five ETM trace pins - are used also as GPIO. 
Five JTAG pins (TRSTX, TCK, TMS, TDI, and TDO) are initially dedicated to debug function, 
whereas five ETM pins (TRACED0, TRACED1, TRACED2, TRACED3, and TRACECLK) are 
not initially dedicated to that. 
When using this series, please configure these ETM pins to provide the debug function. 
Note:  For details on how to set the debug function, see Chapter I/O...