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Fujitsu Series 3 Manual

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Page 1371

 
1. Register Map 
 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
DDR8[B,H,W] 0x220 
---- ---- ---- ---- 0000 0000 0000 0000 
0x224 - 0x2FF - -  - - 
PDIR0[B,H,W] 0x300 
---- ---- ---- ---- 0000 0000 0000 0000 
PDIR1[B,H,W] 0x304 ---- ---- ---- ---- 0000 0000 0000 0000 
PDIR2[B,H,W] 0x308 
---- ---- ---- ---- 0000 0000 0000 0000 
PDIR3[B,H,W] 0x30C  ---- ---- ---- ---- 0000 0000 0000 0000 
PDIR4[B,H,W] 0x310 
---- ---- ---- ---- 0000 0000 0000 0000 
PDIR5[B,H,W] 0x314 ---- ---- ---- ---- 0000 0000...

Page 1372

 
1. Register Map 
 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
0x60C * 
EPFR04[B,H,W] 0x610 
--00 0000 --00 00-- --00 0000 --00 00-- 
EPFR05[B,H,W] 0x614 
--00 0000 --00 00-- --00 0000 --00 00-- 
EPFR06[B,H,W] 0x618 0000 0000 0000 0000 0000 0000 0000 0000 
EPFR07[B,H,W] 0x61C  ---- 0000 0000 0000 0000 0000 0000 ---- 
EPFR08[B,H,W] 0x620 
---- 0000 0000 0000 0000 0000 0000 0000 
EPFR09[B,H,W] 0x624 0000 0000 0000 0000 0000 0000 0000 0000 
EPFR10[B,H,W] 0x628 
0000 0000 0000 0000 0000 0000 0000 0000...

Page 1373

 
1. Register Map 
 
USB Clock  Base_Address : 0x4003_6000 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
UCCR[B,H,W] 0x000 -  - - 
------00 
UPCR1[B,H,W] 0x004 -  - - 
------00 
UPCR2[B,H,W] 0x008 -  - - 
----000 
UPCR3[B,H,W] 0x00C -  - - 
---00000 
UPCR4[B,H,W] 0x010 -  - - 
---10111 
UP_STR[B,H,W] 0x014 -  - - 
-------0 
UPINT_ENR[B,H,W]0x018 -  - - 
-------0 
UPINT_CLR[B,H,W]0x01C -  - - 
-------0 
UPIN_STR[B,H,W]0x020 -  - - 
-------0 
0x024 - 0x02F  - -  - - 
USBEN[B,H,W] 0x030 -  - - 
-------0...

Page 1374

 
1. Register Map 
 
MFS ch4  Base_Address : 0x4003_8400 
MFS ch5  Base_Address : 0x4003_8500 
MFS ch6  Base_Address : 0x4003_8600 
MFS ch7  Base_Address : 0x4003_8700 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
SCR / 
IBCR[B,H,W]  SMR[B,H,W] 0x0000 - 
- 
0--0000 000000-0 
ESCR / SSR[B,H,W]  IBSR[B,H,W] 0x0004 -  - 
0-00011 0000000 
RDR/TDR[H,W] 0x0008 -  - 
-----0 00000000 
BGR1[B,H,W] BGR0[B,H,W] 0x000C -  - 
00000000 00000000 
ISMK[B,H,W] ISBA[B,H,W] 0x0010 -  - 
-------- -------- 
FCR1[B,H,W]...

Page 1375

 
1. Register Map 
 
EXT-Bus I/F  Base_Address : 0x4003_F000 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
MODE0[W] 0x0000 
-------- -------- -------- -0000000 
MODE1[W] 0x0004 -------- -------- -------- -0000000 
MODE2[W] 0x0008 
-------- -------- -------- -0000000 
MODE3[W] 0x000C  -------- -------- -------- -0000000 
MODE4[W] 0x0010 -------- -------- -------- -0000000 
MODE5[W] 0x0014 
-------- -------- -------- -0000000 
MODE6[W] 0x0018 -------- -------- -------- -0000000 
MODE7[W] 0x001C...

Page 1376

 
1. Register Map 
 
USB ch0  Base_Address : 0x4004_0000 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
HCNT1[B,H,W] HCNT0[B,H,W] 0x2100 -  - 
-----001 00000000 
HERR[B,H,W] HIRQ[B,H,W] 0x2104 -  - 
00000011 0-000000 
HFCOMP[B,H,W] HSTATE[B,H,W] 0x2108 -  - 
00000000 --010010 
HRTIMER(1/0)[B,H,W] 0x210C -  - 
00000000 00000000 
HADR[B,H,W] HRTIMER(2)[B,H,W]0x2110 -  - 
-0000000 -----00 
HEOF(1/0)[B,H,W] 0x2114 -  - 
--000000 00000000 
HFRAME(1/0)[B,H,W] 0x2118 -  - 
-----000 00000000 
HTOKEN[B,H,W]...

Page 1377

 
1. Register Map 
 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
EP0DTH[B,H,W] EP0DTL[B,H,W] 0x2160 -  - 
XXXXXXXX XXXXXXXX 
EP1DTH[B,H,W] EP1DTL[B,H,W] 0x2164 -  - 
XXXXXXXX XXXXXXXX 
EP2DTH[B,H,W] EP2DTL[B,H,W] 0x2168 -  - 
XXXXXXXX XXXXXXXX 
EP3DTH[B,H,W] EP3DTL[B,H,W] 0x216C -  - 
XXXXXXXX XXXXXXXX 
EP4DTH[B,H,W] EP4DTL[B,H,W] 0x2170 -  - 
XXXXXXXX XXXXXXXX 
EP5DTH[B,H,W] EP5DTL[B,H,W] 0x2174 -  - 
XXXXXXXX XXXXXXXX 
0x2178 - 
0xFFFF  - - - - 
 
FUJITSU SEMICONDUCTOR LIMITED 
APPENDIXES...

Page 1378

 
1. Register Map 
 
DMAC Base_Address : 0x4006_0000 
 
Base_Address 
Register 
+ Address +3  +2 +1 +0 
DMACR[B,H,W] 0x0000 
00-00000 -------- -------- -------- 
DMACA0[B,H,W] 0x0010 00000000 0---0000 00000000 00000000 
DMACB0[B,H,W] 0x0014 
--000000 00000000 00000000 --------0 
DMACSA0[B,H,W] 0x0018 00000000 00000000 00000000 00000000 
DMACDA0[B,H,W] 0x001C  00000000 00000000 00000000 00000000 
DMACA1[B,H,W] 0x0020 
00000000 0---0000 00000000 00000000 
DMACB1[B,H,W] 0x0024  --000000 00000000 00000000...

Page 1379

 
1. Register Map 
 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
DMACA6[B,H,W] 0x0070 
00000000 0---0000 00000000 00000000 
DMACB6[B,H,W] 0x0074  --000000 00000000 00000000 --------0 
DMACSA6[B,H,W] 0x0078 
00000000 00000000 00000000 00000000 
DMACDA6[B,H,W] 0x007C  00000000 00000000 00000000 00000000 
DMACA7[B,H,W] 0x0080  00000000 0---0000 00000000 00000000 
DMACB7[B,H,W] 0x0084 
--000000 00000000 00000000 --------0 
DMACSA7[B,H,W] 0x0088 00000000 00000000 00000000 00000000 
DMACDA7[B,H,W] 0x008C...

Page 1380

 
1. Register Map 
 
CAN ch0  Base_Address : 0x4006_2000 
CAN ch1  Base_Address : 0x4006_3000 
 Base_Address 
Register 
+ Address +3  +2 +1 +0 
STATR[B,H,W] CTRLR[B,H,W] 0x0000 
-------- 00000000 -------- 000-0001 
BTR[B,H,W] ERRCNT[B,H,W] 0x0004 
-0100011 00000001 00000000 00000000 
TESTR[B,H,W] INTR[B,H,W] 0x0008  -------- X00000-- 00000000 00000000 
BRPER[B,H,W] 0x000C -  - 
-------- ----0000 
IF1CMSK[B,H,W] IF1CREQ[B,H,W] 0x0010 
-------- 00000000 0------- 00000001 
IF1MSK2[B,H,W] IF1MSK1[B,H,W]...

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