Fujitsu Series 3 Manual

 
5. Endianness and Valid Byte Lanes 
 
Example: 
When a byte access is performed to a 16-bit wide target, only 2 bytes are valid according to endianness 
shown in the above table. Data in the internal bus is assigned to 16 bits according to endianness, and input 
or output. 
 
31 0
23 15 7
Unused
Little endian
HADDR[1]=0
310
23 15 7
H*DATA
External I/O
MDATA HADDR[1]=1
 
 
HADDR: AHB address input 
As shown in the above figure, only HADDR[1] is involved in data assignment. This is also the case with...

 
5. Endianness and Valid Byte Lanes 
 
The following figure shows a correlation between internal data and ex ternal I/O when the 8-bit wide target 
is accessed. 
Only a single byte is valid according to endianness. 
 
31
Unused
HADDR[1:0]= 10
HADDR[1:0]=01HADDR[1:0]=11  HADDR[1:0]=00
23 15
70
31 23 15 70
Internal bus data
H*DATA
External I/O
MDATA
Little endian
 
 
For an 8-bit target, the HADDR[1:0] value determines the I/O data. 
When a word or half word access is performed, the ex
ternal bus...

 
6. Connection Examples 
 
6. Connection Examples 
This section provides an example of connections with external devices. 
 8-bit SRAM 
Figure 6-1  shows an example of connecting an 8-bit SRAM. 
Figure 6-1 Example 8-bit SRAM connection 
 
This LSI
x8 SRAM
MAD [24:0]
MCSX [0] MOEX
MWEX
MDATA [7:0] Adr
CS
OE
WE
DQ [7:0]
 
 

 8-bit SRAM   2 
Figure 6-2  shows an example of connecting two 8-bit SRAMs. 
Figure 6-2 Example dual 8-bit SRAMx2 connection 
 
This LSI
x8 SRAM
x8 SRAM
MDATA  [7:0]
MDATA...

 
6. Connection Examples 
 
 16-bit SRAM 
Figure 6-3  shows an example of connecting a 16-bit SRAM. 
Figure 6-3 Example 16-bit SRAM connection 
 
This LSI
X16 SRAM
 
 MAD [24:1]
MCSX [0] MOEX
MWEX
MDQM [1:0]
MDATA [15:0] A
CS
OE
WE
DQM [1:0]
DQ [15:0]
 
 
  8-bit NAND 
Figure 6-4  shows an example of connecting an 8-bit NAND flash memory. 
Figure 6-4 Example 8-bit NAND flash memory connection 
 
This LSI
x8 NAND
MAD [24:0]
MCSX [0] MNCLE
MNALE
MNREX
MNWEX
MDATA [7:0] A
CS
CLE
ALE
RE
WE
DQ [7:0]...

 
7. Registers 
 
7. Registers 
This section explains the configuration and functions of registers used for the external bus 
interface. 
The following explains the registers used for the external bus interface. The bit width of every register is 32. 
Each register can be accessed by the APB interface w ith 32-bit width (word). Write 0 to reserved areas. 
A rewritten register value is not immediately applied  to the operation. When you rewrite a register value 
during access to an external memory, the...

 
7. Registers 
 
7.1.  Mode Register 0 to Mode Register 7 
The following shows the configuration of the Mode Register (0 to 7). 
 
bit 31 30 29 28 27 26 25242322 21 20 19 18 17 16 
Field Reserved 
Attribute - 
Initial  value  - 
                 
bit 15 14 13 12 11 10 9 876 5 4 3 2 1 0 
Field Reserved TESTPAGENAND
WEOFF RBMON WDTH 
Attribute -  R/WR/W 
Initial 
value  - 0 0 0 0 0 0*1 
 
[bit 6] TEST 
Always set this bit to 0. It must not be set to 1. 
The read value is 0. 
 
[bit 5] PAGE (PAGE access...

 
7. Registers 
 
[bit 3] WEOFF (WEX OFF): Write Enable OFF 
This bit can disable the write enable signal (MWEX) operation. 
When the byte mask signal (MDQM) is used as a de vice write enable signal, disabling unnecessary MWEX 
operation can reduce current consumption. When this bit is set to disable, MWEX is fixed to HIGH. 
Bit Description 
0  Enable [Initial value] 
1 Disable 
 
[bit 2] RBMON: Read Byte Mask ON 
This bit can enable the byte mask signal (MDQM) for read access. 
The setting controls the...

 
7. Registers 
 
7.2.  Timing Register 0 to Timing Register 7 
The following shows the configuration of the Timing Register (0 to 7). 
 
bit 31 30 29 28 27 2625242322212019 18 17 16
Field WIDLC WWEC WADC WACC 
Attribute R/W 
Initial  value  0000 0101 0101 1111 
                 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field RIDLC FRADC RADC RACC 
Attribute R/W 
Initial  value  1111 0000 0000 1111 
 
[bit 31:28] WIDLC: Write Idle Cycle 
These bits set the number of idle cycles after write access. 
Bit...

 
7. Registers 
 
[bit 23:20] WADC: Write Address Setup cycle 
These bits set the number of setup cycles of write address. 
The address is output during the cycle set by these bits, but a write enable signal is not asserted until the set 
cycle starts. 
Bit 23 Bit 22 Bit 21 Bit 20 Description 
0 0 0 0 1 cycle 
...  ... 
0  1 0 1 6 cycles [Initial value] 
... 
... 
1 1 1  0 15 cycles 
1 1 1  1 Setting disabled 
 
[bit 19:16] WACC: Write Access Cycle 
These bits set the number of cycles required for write...

 
7. Registers 
 
[bit 11:8] FRADC: First Read Address Cycle 
These bits exclusively set a NOR flash memory that supports page mode access. 
They set the initial wait time of the address during read access to flash memory. 
The address for the set cycle is retained only during  the first cycle. After the first access, the access is 
performed according to the numb er of cycles set by RACC. 
In page mode access, MCSX and MOEX are asserted simultaneously. 
If values other than 0 is set to these bits , set...