Fujitsu Series 3 Manual

 
4. CAN Registers 
 
4.5.2. CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) 
The CAN New Data Register indicates the NewDat bit of all message objects. This register 
checks which message object data is updated by reading the NewDat bit. 
 Register configuration 
- CAN New Data Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field NewDat32-25 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN New Data Register 2 (Low-order byte)  bit  7 6 5  4 3 2 1 0...

 
4. CAN Registers 
 
  Resetting conditions 
   Set 0 to the WR/RD bit of the IFx Command Mask  Register and 1 to the NewDat bit, and write 
data to the IFx Command Request Register to re set the NewDat bit of a specific message object. 
   Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 0 to 
the NewDat bit of the IFx Message Control Register. Then write data to the IFx Command Request 
Register to reset the NewDat bit of a specific message object. 
   The...

 
4. CAN Registers 
 
4.5.3. CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) 
The CAN Interrupt Pending Register indicates the IntPnd bit of all message objects. This 
register checks which message object is pending for interrupt by reading the IntPnd bit. 
 Register configuration 
- CAN Interrupt Pending Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field IntPnd32-25 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Interrupt Pending...

 
4. CAN Registers 
 
  Resetting conditions 
   Set 0 to the WR/RD bit of the IFx Command Mask Re gister and 1 to the CIP bit, and write data to 
the IFx Command Request Register to reset th e IntPnd bit of a specific message object. 
   Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 0 to 
the IntPnd bit of the IFx Message Control Register. Then write data to the IFx Command Request 
Register to reset the IntPnd  bit of a specific message object. 
 
FUJITSU...

 
4. CAN Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: CAN Controller 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  68 
4.5.4. CAN Message Valid Registers 1, 2 (MSGVAL1,  MSGVAL2) 
The CAN Message Valid Register indicates the MsgVal bit of all message objects. This 
register checks which message object is valid by reading the MsgVal bit. 
 Register configuration 
- CAN Message Valid Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field MsgVal32-25 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
1260 
MB9Axxx/MB9Bxxx  Series  

 
1. CRC Overview 
 
Chapter: CRC (Cyclic Redundancy Check) 
This chapter explains the CRC functions. 
 
1.
 CRC Overview 
2. CRC Operations 
3. CRC Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FS15-E02.1 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
1261 
MB9Axxx/MB9Bxxx  Series  

 
1. CRC Overview 
 
1. CRC Overview 
The CRC (Cyclic Redundancy Check) is an error detection system. The CRC code is a 
remainder after an input data string is divided by the pre-defined generator polynomial, 
assuming the input data string is a high order polynomial. Ordinarily, a data string is suffixed 
by a CRC code when being sent, and the receiv ed data is divided by a generator polynomial 
as described above. If the received data is dividable, it is judged to be correct. 
  CRC functions 
This...

 
2. CRC Operations 
 
2. CRC Operations 
This section provides an overview of CRC operations. 
  CRC definition 
[CCITT CRC16 Standard] 
 Generator polynomial 0x1021  (CRCCR. CRC32=0) 
 Initial value  0xFFFF 
  Final XOR value  0x0000  (CRCCR. FXOR=0) 
  Bit order  MSB First  (CRCCR. LSBFST=0) 
  Output bit order  MSB First  (CRCCR. CRCLSF=0) 
  (The input-output byte order can be specified arbitrarily.) 
[IEEE-802.3 CRC32 Ethernet Standard] 
 Generator polynomial 0x04C11DB7 (CRCCR. CRC32=1) 
 Initial...

 
2. CRC Operations 
 
2.1.  CRC calculation sequence 
Figure 2-1  shows the CRC calculation sequence. In this section, it is assumed that the Initial 
Value Register (CRCINIT) setting, CRC16 or CRC32 mode selection (CRCCR.CRC32), and 
byte- or bit-order setting (CRCCR.LTLEND,  CRCCR.LSBFST) have already been configured. 
(If the initial value can be set to ALLH, the Initial Value Register (CRCINIT) setting can be 
omitted.) 
 
Figure 2-1 CRC calculation sequence 
 
:CRC :DMA :CPU
Initialization ()
CRC...