Fujitsu Series 3 Manual

 
4. CAN Registers 
 
4. CAN Registers 
The following registers are provided for CAN. 
- CAN Control Register (CTRLR) 
- CAN Status Register (S
TATR) 
- CAN Error Counter (ERRCNT) 
- CAN Bit Timing Register (BTR) 
- CAN Interrupt Register (INTR) 
- CAN Test Register (TESTR) 
- CAN Prescaler Extension Register (BRPER) 
- IFx Command Request Register (IFxCREQ) 
- IFx Command Mask Register (IFxCMSK) 
- IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) 
- IFx Arbitration 1, 2 (IFxARB1, IFxARB2) 
- IFx Message...

 
4. CAN Registers 
 
 Message interface register list 
Table 4-2 Message interface register list 
Abbreviation Register name See 
IF1CREQ  IF1 Command Request Register  4.3.1 
IF1CMSK IF1 Command Mask Register  4.3.2 
IF1MSK1 IF1 Mask Register 1  4.3.3 
IF1MSK2 IF1 Mask Register 2  4.3.3 
IF1ARB1 IF1 Arbitration Register 1  4.3.4 
IF1ARB2 IF1 Arbitration Register 2 4.3.4 
IF1MCTR IF1 Message Control Register  4.3.5 
IF1DTA1 IF1 Data A Register 1 (Little endian)  4.3.6 
IF1DTA2 IF1 Data A Register 2...

 
4. CAN Registers 
 
 Message handler register list 
Table 4-3 Message handler register list 
Abbreviation Register name See 
TREQ1  CAN Transmit Request Register 1  4.5.1 
TREQ2 CAN Transmit Request Register 2  4.5.1 
NEWDT1 CAN New Data Register 1  4.5.2 
NEWDT2 CAN New Data Register 2  4.5.2 
INTPND1 CAN Interrupt Pending Register 1  4.5.3 
INTPND2 CAN Interrupt Pending Register 2  4.5.3 
MSGVAL1 CAN Message Valid Register 1  4.5.4 
MSGVAL2 CAN Message Valid Register 2  4.5.4 
 
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4. CAN Registers 
 
4.1.  CAN register functions 
An address space of 256 bytes is allocated the CAN register. The CPU gains access to the 
message RAM via the message interface registers. 
This section lists CAN registers, and describes the detailed function of each register. 
 Total control registers 
  CAN Control Register (CTRLR) 
   CAN Status Register (STATR) 
   CAN Error Counter (ERRCNT) 
   CAN Bit Timing Register (BTR) 
   CAN Interrupt Register (INTR) 
   CAN Test Register (TESTR) 
...

 
4. CAN Registers 
 
4.2.  Total control registers 
Total control registers control the CAN protocol and operating modes, and p\
rovide status 
information. 
 Total control registers 
  CAN Control Register (CTRLR) 
   CAN Status Register (STATR) 
   CAN Error Counter (ERRCNT) 
   CAN Bit Timing Register (BTR) 
   CAN Interrupt Register (INTR) 
   CAN Test Register (TESTR) 
   CAN Prescaler Extension Register (BRPER) 
 
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CHAPTER  21-2: CAN Controller...

 
4. CAN Registers 
 
4.2.1. CAN Control Register (CTRLR) 
The CAN Control Register controls the operating modes of the CAN controller. 
 Register configuration 
- CAN Control Register (high-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Control Register (low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Test  CCE DAR Reserved EIE SIE  IE...

 
4. CAN Registers 
 
[bit 5] DAR: Automatic retransmission disable bit 
Bit Function 
0 Enables automatic retransmission when arbitration is lost or an error is detected. 
[Initial value] 
1 
Disables automatic retransmission. 
 
Based on the CAN specification (ISO11898. See 6.3.3 Recovery Sequence), the CAN controller 
automatically resends frames when arbitration is lost or  an error is detected during transfer. To allow the 
automatic retransmission, set the DAR bit to 0.  To operate CAN in Time...

 
4. CAN Registers 
 
[bit 3] EIE: Error interrupt code enable bit 
Bit Function 
0 A change of the BOff or EWarn bit in th
e CAN Status Register disables the setting 
of interrupt code in the CAN Interrupt Register. 
[Initial value] 
1  A change of the BOff or EWarn bit in th
e CAN Status Register enables the setting 
of status interrupt code in the CAN Interrupt Register. 
 
[bit 2] SIE: Status interrupt code enable bit 
Bit Function 
0  A change of the TxOk, RxOk, or LEC bit in the CAN Status Register...

 
4. CAN Registers 
 
   The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or 
resetting the 

Init bit. If the device enters busoff state, the CAN controller itself sets the Init bit to 1, 
stopping all bus operations. If the Init bit is cleared to 0 from the busoff state, the bus operation 
remains stopped until 129 bus idle sequences (one bus  idle sequence consists of 11 recessive bits) occur 
consecutively. When the bus recovery sequence  has completed,...

 
4. CAN Registers 
 
4.2.2. CAN Status Register (STATR) 
The CAN Status Register indicates the CAN status and a CAN bus state. 
 Register configuration 
- CAN Status Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Status Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field BOff  EWarn EPass RxOk  TxOk  LEC 
Attribute...