Fujitsu Series 3 Manual

 
4. CAN Registers 
 
4.3.1. IFx Command Request Register (IFxCREQ) 
The IFx Command Request Register is used to select a message number of the message 
RAM and transfer data between the message RAM and Message Buffer Register. In basic 
test mode, IF1 is used to control sending and IF2 to control receiving. 
 Register configuration 
- IFx Command Request Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field BUSY Reserved ReservedReservedReservedReserved Reserved Reserved
Attribute R/W  R0,W0...

 
4. CAN Registers 
 
  Basic test mode 
   IF1 Command Request Register 
Bit Function 
0  Disables message sending. 
1 Enables message sending. 
 
  IF2 Command Request Register 
Bit Function 
0 Disables message receiving. 
1 Enables message receiving. 
 
[bit 14:8] Reserved bits  Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7:0] Message Number: Message number (32 message buffers) 
Bit 7:0  Function 
0x00, 0x40, 0x60, 0x80,   
0xA0, 0xC0, 0xE0  Setting disabled. 
If...

 
4. CAN Registers 
 
4.3.2. IFx Command Mask Register (IFxCMSK) 
The IFx Command Mask Register is used to control the transfer direction between the 
Message Interface Register and message RAM and specify which data is to be updated. This 
register is invalid in basic test mode. 
 Register configuration 
- IFx Command Mask Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0...

 
4. CAN Registers 
 
 When the transfer directi on is writing (WR/RD=1) 
[bit 6] Mask: Mask data update bit 
Bit Function 
0 Indicates that mask data (ID mask + MDir + MXtd) of a message object*1 is not 
updated. [Initial value] 
1 Indicates that mask data (ID mask + 
MDir + MXtd) of a message object*1 is 
updated. 
*1: See  4.4 Message objects . 
 
[bit 5]  Arb: Arbitration data update bit 
Bit Function 
0  Indicates that arbitration data (ID + Dir + Xtd + MsgVal) of a message object*1 is 
not...

 
4. CAN Registers 
 
[bit 1] Data A: Data 0-3 update bit 
Bit Function 
0 Indicates that data 0-3 of a me
ssage object*1 is not updated. 
[Initial value] 
1  Indicates that data 0-3 of a message object*1 is updated. 
*1: See 4.4 Message objects . 
 
[bit 0] Dat a B: Data 4-
7 update bit 
Bit Function 
0  Indicates that data 4-7 of a me
ssage object*1 is not updated. 
[Initial value] 
1  Indicates that data 4-7 of a message object*1 is updated. 
*1: See 4.4 Message objects . 
 
 
  When  t

he TxRqst or...

 
4. CAN Registers 
 
 When the transfer directi on is reading (WR/RD=0) 
[bit 6] Mask: Mask data update bit 
Bit Function 
0 Indicates that data (ID mask + MDir + 
MXtd) is not transferred from a message 
object*1 to IFx Master Register 1 or 2.    [Initial value] 
1  Indicates that data (ID mask + MDir 
+ MXtd) is transferred from a message 
object*1 to IFx Master Register 1 or 2. 
*1: See  4.4 Message objects . 
 
[bit 5]  Arb: Arbitration data update bit 
Bit Function 
0  Indicates that data (ID +...

 
4. CAN Registers 
 
[bit 1] Data A: Data 0-3 update bit 
Bit Function 
0 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is 
held.  [Initial value] 
1  Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is 
updated. 
*1: See  4.4 Message objects . 
 
[bit 0] Dat a B: Data 4-
7 update bit 
Bit Function 
0  Indicates that data of the message object
*1 and CAN Data Register B1 or B2 is 
held.  [Initial value] 
1  Indicates that data of the message...

 
4. CAN Registers 
 
4.3.3. IFx Mask Registers 1, 2 (IFxMSK1 ,IFxMSK2) 
The IFx Mask Registers 1 and 2 are used to write or read message object mask data of the 
message RAM. The specified mask data is invalid in basic test mode. 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx Mask Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field MXtd MDir ReservedMsk28-24 
Attribute  R/W R/W  R1,W1 R/W R/W R/W  R/W R/W 
Initial value 1 1 1  1 1 1 1 1 
 
- IFx Mask...

 
4. CAN Registers 
 
4.3.4. IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2) 
The IFx Arbitration Registers 1 and 2 are used to write or read message object arbitration data 
of the message RAM. This register is invalid in basic test mode. 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx Arbitration Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field MsgValXtd Dir ID28-24 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0...

 
4. CAN Registers 
 
4.3.5. IFx Message Control Register (IFxMCTR) 
The IFx Message Control Register is used to write or read message object control data of the 
message RAM. This register is invalid in basic test mode. The NewDat and MsgLst bits of the 
IF2 Message Control Register are used to perform normal operations. The DLC bits indicate 
the DLC of the received message. The other control bits are invalid (0). 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx...