Fujitsu Series 3 Manual

 
3. CAN Controller Operations 
 
3.4.  FIFO buffer function 
The following explains the configuration of a FIFO buffer of the message object and its 
operations in handling received messages. 
 Configuration of a FIFO buffer 
The configuration of the receive message object belonging  to a FIFO buffer is the same as that of a receive 
message object except the EoB bit. (See Co nfiguring a Receive Message Object in 3.3 Message 
reception .) 
A  FIFO buffer 
is use

d by concatenating two or more receive...

 
3. CAN Controller Operations 
 
 Reading from a FIFO buffer 
To read the contents of a receive message object, th e CPU transfers the object to the Message Interface 
Register by writing the received message number to  the IFx Command Request Register. Then, set WR/RD 
in the IFx Command Mask Register to 0 (read), set TxRqst/NewDat = 1, ClrIntPnd = 1, and set the 
NewDat bit and IntPnd bit to 0. 
To assure the correct FIFO buffer function, be sure to  first read a receive message object in the FIFO...

 
3. CAN Controller Operations 
 
3.5. Interrupt function 
The following explains the interrupt handing using the status interrupt (IntId = 0x8000) and 
message interrupt (IntId = Message number). 
If two or more interrupts are pending, the CAN Interrupt Register points to a pending interrupt code with 
the highest priority. The chronological order of the interrupt codes are neglected, and the interrupt code with 
the highest priority is always shown. The interrupt code is retained until the CPU clears...

 
3. CAN Controller Operations 
 
3.6. Bit timing 
The following provides the overview of the bit timing and explains about the bit timing in the 
CAN controller. 
Each CAN node in the CAN network has its own clock generator (usually a quartz oscillator). The time 
parameter of the bit time can be configured indivi dually for each CAN node. Even if each CAN nodes 
oscillator has a different period (fosc), a common bit rate can be generated. 
The oscillator frequencies vary slightly because of changes in...

 
3. CAN Controller Operations 
 
Table 3-3 CAN bit time parameters Parameter Range Function 
BRP  [1-32] Defines the length of time quantum tq. 
Sync_Seg  1 tq Fixed length. Synchronization to system clock. 
Prop_Seg  [1-8] tq Compensates for the physical delay times. 
Phase_Seg1 [1-8] tq  Assures edge phase errors before the sampling point. 
May be prolonged temporarily by synchronization. 
Phase_Seg2 [1-8] tq Assures edge phase errors after the sampling point. 
May be shortened temporarily by...

 
3. CAN Controller Operations 
 
3.7. Test mode 
The following explains how to configure test mode, and about its operations. 
 Test mode setting 
Test mode is entered by setting the Test bit in the CAN Control Register to 1. In test mode, the Tx1, Tx0, 
LBack, Silent, and Basic bits in th e CAN Test Register are enabled. 
When the Test bit in the CAN Control Register is set to 0, all test register functions are disabled. 
  Silent mode 
The CAN controller can be set in silent mode by programming the...

 
3. CAN Controller Operations 
 
 Loop back mode 
The CAN controller can be set in loop back mode by programming the LBack bit in the CAN Test Register 
to 1. 
Loop back mode can be used for self-diagnostic functions. 
In loop back mode, TX is connected with RX inside the CAN controller. The CAN controller treats the 
transmitted messages as messages received by RX, and  stores the messages passed acceptance filtering into 
the receive buffer. 
Figure 3-6  shows the connection of the CAN_TX and CAN_RX...

 
3. CAN Controller Operations 
 
 Combination of silent mode and loop back mode 
Loop back mode and silent mode can be combined by setting the LBack bit and Silent bit in the CAN Test 
Register to 1 at the same time. 
This mode can be used for Hot self-test. The Hot self-test means that the CAN controller can be tested 
in loop back mode without affec ting operation of the CAN system, becau se a constant recessive value is 
output from the CAN_TX pin and the input to the CAN_RX pin is ignored. 
Figure...

 
3. CAN Controller Operations 
 
The IF2 Message Interface Register is used to control reception. 
All contents of the message are received without using acceptance filteri ng. The contents of the received 
message can be read by setting the Busy bit in the IF2 Command Request Register to 1. 
When the Busy bit is set to 1, the CAN controller performs the following operation: 
   Stores the received message (the  contents of the receive shift register) into the IF2 Message Interface 
Register without...

 
3. CAN Controller Operations 
 
3.8. Software initialization 
The following explains about initialization using software. 
The sources of software initialization are as follows: 
  Hardware reset 
   Setting the Init bit in the CAN Control Register 
   Shift to a busoff state 
 
A hardware reset resets all other than the message RAM (excluding the MsgVal, NewDat, IntPnd, and 
TxRqst bits). The message RAM must be initialized, afte r the hardware reset, by the CPU or by setting the 
MsgVal in the...