Fujitsu Series 3 Manual

 
5. USB host registers 
 
[bit 10] STUFF (STUFFing error) 
This is a stuffing error flag. 
If this bit is set to 1, it means that a bit stuffing error is detected. When this bit is 0, it means that no 
stuffing error is detected. If a stuffing error is detected, bit 5 (Timeout) of this register is also set to 1. If 
this bit is written with 0, it is set to 0. However,  if this bit is written with 1, its value is ignored. 
Bit Description 
0 No stuffing error. 
1 Stuffing error occurs. 
 
 
This  b

it...

 
5. USB host registers 
 
5.4.  Host Status Register (HSTATE) 
The Host Status Register (HSTATE) indicates the state of the USB circuit such as a device 
connection or transfer mode. Note that the setting of the CLKSEL bit is also effective in the 
function mode. 
 bit 7 6 5 4 3 2 1 0 
Field ReservedReserved ALIVECLKSELSOFBUSYSUSP TMODE CSTAT 
Attribute  - R/W R/W R/W R/W  R R 
Initial value  X 0 1 0 0  1 0 
Reset enabled    or not*  - x 
x  x x 
      
* : Enables or disables a reset with the  RST bit...

 
5. USB host registers 
 
[bit 3] SOFBUSY (SOF BUSY) 
This is a SOF busy flag. 
When a SOF token is sent using the Host Token Endpoint Register (HTOKEN), this bit is set to 1, which 
means that the SOF timer is active. When this bit is 0, it means that the SOF timer is under suspension. To 
stop the active SOF timer, write 0 to this bit. However,  if this bit is written with 1, its value is ignored. 
Bit Description 
0 The SOF timer is stopped. 
1  The SOF timer is active. 
 
 

 This bit is set to the...

 
5. USB host registers 
 
[bit 1] TMODE (Transmission MODE) 
This is a transmission mode flag. 
If this bit is 1, it means that the device is connected in the full-speed mode. When this bit is 0, it means 
that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status 
Register (HSTATE) is 1. 
Bit Description 
0 Low Speed 
1 Full Speed 
 
 
 This bit is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Use the base clock...

 
5. USB host registers 
 
5.5.  SOF Interrupt Frame Compare Register (HFCOMP) 
The SOF Interrupt Frame Compare Register (HFCOMP) is used to specify the data to be 
compared with the low-order eight bits of a frame number when sending a SOF token. When 
the SOFSTEP bit of Host Control Register 0 (HCNT0) is 0, the value of this register is 
comp
ared with that of the low-order eight bits of a frame number. If they match, the SOFIRQ 
bit of the Host interrupt Register (HIRQ) is set to 1 when starting SOF...

 
5. USB host registers 
 
5.6.  Retry Timer Setup Register (HRTIMER) 
The Retry Timer Setup Register (HRTIMER) is used to specify the token retry time. 
 bit 15 14 13 12 11 10 9 8 
Field RTIMER1 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
  bit  7 6 5  4 3 2 1 0 
Field RTIMER0 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with...

 
5. USB host registers 
 
5.7. Host Address Register (HADR) 
The Host Address Register (HADR) is used as an address field to send a token. 
 bit 15 14 13 12 11 10 9 8 
Field ReservedAddress 
Attribute -  R/W 
Initial value X  0000000 
Reset enabled    or not*  - x 
* : Enables or disables a reset with the RST bit of  UDCC. x: Not to be reset. o: To be reset. 
 
[bit 15] Reserved bit 
This is a reserved bit. This bits is undefined in read  mode. Even if 0 or 1 is written to this bit, it has no 
effect on...

 
5. USB host registers 
 
5.8.  EOF Setup Register (HEOF) 
The EOF Setup Register (HEOF) is used to specify the token disable time before sending a 
SOF token. If both the following conditions are satisfied, a request token is sent after a SOF 
token has been transferred. 
- When the value of the SOF timer is comp

ared with that of this register, it is less than the 
value of this register. 
- An IN, OUT, or SETUP token sending request has been issued. 
This is a function to prevent a SOF token...

 
5. USB host registers 
 
5.9.  Frame Setup Register (HFRAME) 
The Frame Setup Register (HFRAME) is used to specify a frame number when sending a 
SOF token. If SOF sending is set to the TKNEN bit of the Host Token Endpoint Register 
(HTOKEN), the SOF timer is activated. Af
ter this, SOF is sent automatically every 1 ms. The 
Frame Setup Register is automatically incremented by one each time SOF is ended. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved FRAME1 
Attribute -  R/W 
Initial value X  000 
Reset...

 
5. USB host registers 
 
5.10.  Host Token Endpoint Register (HTOKEN) 
The Host Token Endpoint Register (HTOKEN) is used to specify toggle, endpoint, and token. 
 bit 7 6 5 4 3 2 1 0 
Field TGGL TKNEN ENDPT 
Attribute R/W  R/W  R/W 
Initial value 0  000  0000 
Reset enabled    or not*   
       
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 7] TGGL (ToGGLe) 
This is a toggle bit. 
This bit is used to set toggle data. Toggle data is sent depending...