Fujitsu Series 3 Manual

 
3. USB host operations 
 
Figure 3-4 SOF timing 
 
1ms
Start of SOF Start of SOF
EOF setting time
EOF setting time
EOF > 1-packet time  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-3: USB Host 
MN706-00002-1v0-E 
1145 
MB9Axxx/MB9Bxxx  Series  

 
3. USB host operations 
 
3.4. Data packet 
When sending a data packet after a token packet, transfer toggle data based on the value of 
the TGGL bit of the Host Token Endpoint Register (HTOKEN). Further, send endpoint 1 or 2 
buffer data, CRC16 data, and EOP
 depending on the value of the DIR bit of the EP1 Control 
Register (EP1C). 
When receiving a data packet, compare the value of the TGGL bit of the Host Token Endpoint 
Register (HTOKEN) with the received toggle data. If they match, the received...

 
3. USB host operations 
 
3.5. Handshake packet 
A handshake packet is used to notify the remote device of the status of the local device. 
 Handshake packet 
A handshake packet sends either one of ACK, NAK, and STALL from the receiving side when it is judged 
that the receiving side is ready to receive data norm ally. If the USB circuit receives a handshake packet, the 
type of the received handshake packet is set to the HS  bit of the Host Error Status Register (HERR). If the 
USB circuit sends a...

 
3. USB host operations 
 
3.6. Retry function 
When a NAK or CRC error occurs at the end of a packet, if 1 is set to the RETRY bit of Host 
Control Register 1 (HCNT1), processing is retr ied repeatedly for the period specified in the 
Retry T
 imer Setting Register (HRTIMER). 
 Retry function 
When an error* other than STALL or device disconnection occurs, the target token is retried if the RETRY 
bit of Host Control Register 1 (HCNT1) is 1. The  following shows the conditions to end retry processing....

 
3. USB host operations 
 
3.7. SOF interrupt 
The SOFIRQ bit of the Host Interrupt Register (HIRQ) is set to 1 at start of SOF depending 
on the setting of the SOFSTEP bit of Host Control Register 1 (HCNT1) and SOF Interrupt 
Frame Compare Register (HFCOMP). If the SOFIRE bit of Host Control Register 0 (HCNT0) 
is 1, an int

errupt occurs. When SOF processing is executed using the Host Token Endpoint 
Register (HTOKEN), the SOFIRQ bit of the Host Interrupt Register (HIRQ) is not set to 1. 
  SOF...

 
3. USB host operations 
 
At this timing, the CMPIRQ bit of the Host Interrupt Register (HIRQ) is not set to 1. When the SOFIRQ 
bit is set to 1, the TCAN bit of the Host Interrupt  Register (HIRQ) indicates that a token is canceled. 
When retrying to send a token, write 0 to the TCAN  bit of the Host Interrupt Register (HIRQ). Then write 
a token to be sent to the TKNEN bit of the Host Token Endpoint Register (HTOKEN). 
If 0 is set to the CANCEL bit of Host Control Register 1 (HCNT1), the token...

 
3. USB host operations 
 
3.8. Error status 
The USB host supports error information. 
 Error status 
1.  Stuffing Error 
If 1 is successively set to six bits, 0 is inserted into one bit. If 1 is successively detected in seven 
bits, it is judged to be Stuffing Error, and the STUFF bit of the Host Error Status Register (HERR) is set 
to 1. To clear this status, writ e 0 to the STUFF bit. If the next token is sent without clearing the 
STUFF bit, a cause is reflected on the STUFF bit when the next...

 
3. USB host operations 
 
3.9. End of packet 
If one packet is ended in the USB host, the CMPIRQ bit of the Host Interrupt Register (HIRQ) 
is set to 1. At this time, if the CMPIRE bit of Host Control Register 0 (HCNT0) is 1, an 
interrupt occurs. 
 Packet end timing 
When one packet ends, the interrupt flag is generated when: 
  The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is (001)b, (010)b, or (011)b 
(SETUP token, IN token, or OUT token). 
Figure 3-8 Timing example 1 when setting the...

 
3. USB host operations 
 
3.10.  Suspend and resume operations 
The USB host supports suspend and resume operations. 
 Suspend operation 
If 1 is set to the SUSP bit of the Host Status Register (HSTATE), the procedure below is performed, and 
the USB circuit is placed  into the suspend state. 
   The USB bus is placed in the high-impedance state. 
   A circuit block with no clock required is stopped. 
 
If the USB circuit is placed in the suspend state, the SU SP bit of the Host Status Register...

 
3. USB host operations 
 
 
  The host pin D+ or D- is placed in the K-state mode. 
Figure 3-11 Resume operation by device (Full-speed mode) 
 
Host pin D+
Host pin D- 20ms
*11.33ms*11-bit time
RWIRQ bit of HIRQ
: Output from USB host
: Output from device
: Drive by pull-up or pull-down resistor
*1: Note that the numeric values above are not guaranteed.
  
 
   A device disconnection is detected. 
Figure 3-12 Resume operation by device disconnection 
 
Disconnection
Host pin D+
Host pin D-
RWKIRQ bit...