Fujitsu Series 3 Manual

 
5. USB Function Registers 
 
5.7.  EP0I Status Register (EP0IS) 
The EP0I Status Register (EP0IS) indicates the status of the Endpoint 0 transfer in the IN 
direction. 
The following figure shows the bit configuration of the EP0I Status Register (EP0IS). bit 15 14 13 12 11 10 9 8 
Field BFINI DRQIIE - - - DRQI - - 
Attribute  R/W R/W -  - - R/W  - - 
Initial value  1 0 X  X X 1 X  X 
BFINI reset  1 Irrelevant  X X X 1 X  X 
  bit  7 6 5  4 3 2 1 0 
Field  - - -  - - - - - 
Attribute - - -  - - - - -...

 
5. USB Function Registers 
 
[bit 13:11] Undefined bits The written value has no effect. The read value is undefined. 
 
[bit 10] DRQI: Send/Receive Data Interrupt Request Bit (Data ReQuest In)  This bit indicates that the IN packet transfer from the EP0 host normally ended and data was read out from 
the send buffer, so that the next send data can be wr itten.The DRQI bit is an interrupt cause, and writing 1 
is ignored.Clear it by writing 0.A read-modify-write access reads the bit as 1. 
Bit...

 
5. USB Function Registers 
 
5.8.  EP0O Status Register (EP0OS) 
The EP0O Status Register (EP0OS) indicates the status of the Endpoint 0 transfer in the OUT 
direction. 
The following figure shows the bit configuration of the EP0O Status Register (EP0OS). bit 15 14 13 12 11 10 9 8 
Field BFINI DRQOIE SPKIE - - DRQO SPK Reserved
Attribute  R/W R/W R/W  - - R/W  R/W  - 
Initial value  1 0 0  X X  0 0 0 
BFINI reset  1 Irrelevant  Irrelevant X X  0 0 0 
  bit  7 6 5  4 3 2 1 0 
Field Reserved SIZE...

 
5. USB Function Registers 
 
[bit 13] SPKIE: Short Packet Interrupt Enable Bit (SPK Interrupt Enable) 
This bit enables interrupts generated by the SPK  interrupt cause of the EP0O Status Register. 
Bit Description 
0 Disables interrupts generated by the SPK cause 
1 Enables interrupts generated by the SPK cause 
 
[bit 12:11] Undefined bits  The written value has no effect. The read value is undefined. 
  [bit 10] DRQO: Receive Data Interr upt Request Bit (Data ReQuest Out) 
This bit indicates that...

 
5. USB Function Registers 
 
5.9.  EP1 to 5 Status Registers (EP1S to EP5S) 
The EP1 to 5 Status Registers (EP1S to EP5S) indicate the status of the Endpoints 1 to 5. 
The following figure shows the bit configuration of the EP1 to 5 Status Registers (EP1S to EP5S). 
 EP1 Status Register (EP1S) 
bit  15 14 13  12 11 10  9 8 
Field BFINI  DRQIE SPKIE Reserved BUSY DRQ  SPK SIZE1 
Attribute  R/W R/W R/W  - R R/W  R/W  R 
Initial value  1 0 0  X 0 0  0 X 
  bit  7 6 5  4 3 2 1 0 
Field SIZE1 
Attribute  R...

 
5. USB Function Registers 
 
[bit 14] DRQIE: Packet Transfer Interrupt Enable Bit (Data ReQuest Interrupt Enable) This bit enables interrupts generated by the DRQ  interrupt cause of the EP1 to EP5 Status Register. 
Bit Description 
0 Disables interrupts generated by the DRQ cause 
1 Enables interrupts generated by the DRQ cause 
 
 
To 

use the automatic buffer transfer mode (DMAE = 1) , set DMA and enables transfer before en
 abling the 
DRQIE bit. 
 
[bit 13] SPKIE: Short Packet Interr upt Enable...

 
5. USB Function Registers 
 
[bit 10] DRQ: Packet Transfer Interrupt Request Bit (Data ReQuest) This bit indicates that the EP1 to EP5 packet transfer has normally ended, and processing of the data is 
required.The DRQ bit is an interrupt cause, and wr iting 1 is ignored.Clear the DRQ bit by writing 0 
while it is 1. A read-modify-wr ite access reads the bit as 1. 
Bit Description 
0 Clears the interrupt cause 
1  Packet transfer normally ended 
 
 
If auto m

atic buffer transfer mode (DMAE = 1) is...

 
5. USB Function Registers 
 
[(EP1: bit 8:7) bit 6:0] SIZE: packet SIZE These bits indicate the number of data bytes written to the receive buffer when OUT packet transfer of EP1 
to EP5 has finished. The SIZE bit is updated to a valid value when the DRQ interrupt cause of the EP1 to 
EP5 Status Registers (EP1S to EP5S) has been set. 
The maximum transfer data size of Endpoints 1 to 5 is as follows: 
EndPoint  Maximum transfer size  Indication range 
1 256 bytes  0x000 to 0x100 
2 to 5 64 bytes  0x00...

 
5. USB Function Registers 
 
5.10.  EP0 to 5 Data Registers (EP0DTH to EP5DTH/EP0DTL to EP5DTL) 
The EP0 to 5 Data Registers (EP0DTH to EP5DTH/EP0DTL to EP5DTL) control writing or 
reading transfer data to/from the send/receive buffer for Endpoints 0 to 5. 
The following figure shows the bit configurati on of the EP0 to 5 Data Registers (EP0DTH to 
EP5DTH/EP0DTL to EP5DTL). 
  EP0DTH to EP5DTH 
bit  15 14 13  12 11 10  9 8 
Field BFDT 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value X X X...

 
5. USB Function Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB Function 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  63 
    The CPU can access the EP0 to 
 5 Data Registers (EP0DTH    to EP5DTH/EP0DTL to EP5DTL) either 
by the byte or by the half-word. 
   Byte access 
First access low-order (EPxDTL) and then high-o rder (EPxDTH). Subsequently, access low-order 
(EPxDTL) and high-order (EPxDTH) alternately. 
   This register must not be accessed  by the bit operation instruction. 
 
Example: Setup...