Fujitsu Series 3 Manual

 
5. USB Function Registers 
 
5.3.  EP1 to 5 Control Registers (EP1C to EP5C) 
The EP1 to 5 Control Registers (EP1C to EP5C) control Endpoints 1 to 5. 
The following figure shows the bit configuration of the EP1 to 5 Control Registers (EP1C to EP5C). 
 EP1 Control Register (EP1C) 
 
bit 15 14 13 12 11 10 9 8 
Field EPEN TYPE DIR DMAE NULE STAL PSK1 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 11  0 0 0  0 1 
  bit  7 6 5  4 3 2 1 0 
Field PSK1 
Attribute  R/W R/W R/W  R/W R/W R/W R/W...

 
5. USB Function Registers 
 
[bit 14:13] TYPE: Endpoint Transfer Type Select Bits (endpoint TYPE) These bits specify the transfer type the Endpoint support. 
Bit 14:13  Description 
00 Setting disabled 
01 Setting disabled 
10 Bulk transfer 
11 Interrupt transfer 
 
[bit 12] DIR: Endpoint Transfer Dire ction Select Bit (endpoint DIRection) 
This bit specifies the transfer  direction the Endpoint support. 
Bit Function operating mode Host operating mode (EP1 and EP2 only)
0 OUT Endpoint  IN Endpoint 
1...

 
5. USB Function Registers 
 
[bit 10] NULE: Null Automatic Transfer Enable Bit (NULl Enable set) When a data transfer request in IN the direction is  received while automatic buffer transfer mode is set 
(DMAE = 1), this bit sets a mode that transfers 0-byte  data automatically upon the detection of the last 
packet transfer. 
Bit Description 
0  Releases the NULL automatic transfer mode 
1  Sets the NULL automatic transfer mode 
 
 
For data transfer in th e 

OUT direction or when automatic buffer...

 
5. USB Function Registers 
 
[EP2 to EP5: bit 8:7] EP2 to EP5 reserved bits In EP2 to EP5, these bits are reserved.Write value s hould always be 0. They are always read as 0. 
 
[(EP1: bit 8:7) bits 6:0] PKS: Packet Si ze Setting Bits (PacKet Size ep1 set) 
This bit specifies the maximum size  transferred by one packet. The following shows the maximum packet 
size that can be specified for Endpoints 1 to 5. 
EndPoint  Maximum transfer size  Configurable range 
1 256 bytes (Odd numbers allowed)  0x001...

 
5. USB Function Registers 
 
5.4.  Time Stamp Register (TMSP) 
The Time Stamp Register (TMSP) indicates the frame number upon the receipt of SOF 
packets. 
The following figure shows the bit configuration of the Time Stamp Register (TMSP). bit 15 14 13 12 11 10 9 8 
Field ReservedReserved Reserved TMSP 
Attribute -  - - R R R 
Initial value  X X  XXX  0 0 0 
RST reset  0 0  Irrelevant 0 0 0 
  bit  7 6 5  4 3 2 1 0 
Field TMSP 
Attribute  R R R  R R R R R 
Initial value 0 0 0  0 0 0 0 0 
RST reset  0 0...

 
5. USB Function Registers 
 
5.5.  UDC Status Register (UDCS) 
The UDC Status Register (UDCS) indicates the bus status during USB communication or the 
reception of specific commands.Each bit except the SETP bit is an interrupt cause, and so 
can generate an interrupt to the CPU if the correspondent interrupt enable bit is enabled. 
The following figure shows the bit configuration of the UDC Status Register (UDCS). bit  7 6 5  4 3 2 1 0 
Field -  - SUSP  SOF BRST  WKUP  SETP CONF 
Attribute  - - R/W...

 
5. USB Function Registers 
 
[bit 3] BRST: Bus Reset Detection Bit (Bus ReSeT) This bit indicates the detection of a USB bus reset.  The BRST bit is an interrupt cause, and writing 1 is 
ignored. Clear it by writing 0. A read-m odify-write access reads the bit as 1. 
Bit Description 
0 USB bus reset undetected.  Clears the interrupt cause. 
1 USB bus reset detected 
 
 
When  t

his bit is detected, initialize the buffer by the BFINI bit in the EP0I Status Register (EP0IS), the 
BFINI bi t

 in the...

 
5. USB Function Registers 
 
[bit 0] CONF: Configuration Detection Bit (CONFigration) This bit indicates that the USB function has been configured. The CONF bit is set when SetConfig of a 
USB command is received successfully. The CONF bit is  an interrupt cause, and writing 1 is ignored. 
Clear it by writing 0.A read-modify-w rite access reads the bit as 1. 
Bit Description 
0 SetConfig undetected. Clears the interrupt cause. 
1 SetConfig detected 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB...

 
5. USB Function Registers 
 
5.6.  UDC Interrupt Enable Register (UDCIE) 
The UDC Interrupt Enable Register (UDCIE) enables each bit (except the CONFN bit), 
interrupts generated by each interrupt cause of the UDC Status  Register
 . 
The following figure shows the bit configuration of the UDC Interrupt Enable Register (UDCIE). 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved SUSPIESOFIE BRSTIEWKUPIE CONFN CONFIE
Attribute  - - R/W  R/W R/W R/W  R R/W 
Initial value  0 0 0  0 0 0 0 0 
RST reset  0...

 
5. USB Function Registers 
 
[bit 10] WKUPIE: Wake-up Interrupt Enable Bit (WKUP Interrupt Enable) 
This bit enables interrupts generated by the WKU P interrupt cause of the UDC Status Register. 
Bit Description 
0 Disables interrupts generated by the WKUP cause 
1 Enables interrupts generated by the WKUP cause 
 
[bit 9] CONFN: Configuration Number Indication Bit (CONFigration Number)  This bit indicates the configuration number. The information is updated when the CONF interrupt cause of 
the UDC...