Fujitsu Series 3 Manual

 
6. LIN Interface (ver. 2.1) Registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: LIN Interface (Ver. 2.1) (LIN Co mmunication Control Interface Ver. 2.1) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  56 
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writing Sets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets  already written in FIFO but not transmitted yet 
During...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
966 
MB9Axxx/MB9Bxxx  Series  

 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: I2C Interface (I2C Communications 
Control Interface) 
This chapter describes the I2C function supported in operation mode 4 of the multifunctional 
serial interface. 
 
1.
 Overview of I2C Interface (I2C Communications Control Interface) 
2. I2C Interface interrupt 
3. Dedicated Baud Rate Generator 
4. I2C communication operation flowchart examples 
5. I2C Interface Registers  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FM15I-E05.2 
CHAPTER  19-5: I2C...

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1.  Overview of I2C Interface (I2C Communications Control 
Interface) 
The I2C interface (I2C communications control interface) supports the I2C bus and operates as 
a master/slave device on the I2C bus. It also has transmit/receive FIFO (up to 128 × 9 bits 
each) *1installed. 
  Functions of I2C interface (I2C communications control interface) 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/receive FIFO (max  128 × 9 bits...

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2. I2C Interface interrupt 
I2C interface interrupt request is generated due to the following factors. 
- After transmission/reception of the first byte and after data transmission/reception is  completed 
- Stop condition 
-  Iteration start condition 
-  FIFO transmit dat

a request 
-  FIFO receive data completed 
  I2C Interface Interrupt 
Ta b l e  2 - 1  shows the interrupt control bits and interrupt causes for the I2C interface. 
Table 2-1 Interrupt control bits and...

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*1 : If normal data can be transmitted/received and SSR:TDRE is 0, no interrupt is generated. This to support DMA transfers. 
To generate an IBCR:INT flag at a time of data tran smission/reception, the SSR:TDRE bit needs to be set to 
1 before the IBCR:INT flag is set. 
*2 : Be sure to check that the SSR:TDRE bit is set to 0 and then set the SMR:TIE bit to 1.   
*3 : Be sure to check that the SSR:TBI bit is set to 0 and then set the SSR:TBIE bit to 1.     
CHAPTER  19-5:...

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2.1. I2C interface operation 
The I2C interface performs communications using two two-way bus lines, a serial data line 
(SDA) and a serial clock line (SCL). 
 I2C bus start condition 
The following shows the I2C bus start condition. 
Figure 2-1 Start condition 
   SD A   
   SCL 
                             Start condition 
 
 
  I2C bus stop condition 
The following shows the I2C bus stop condition. 
Figure 2-2 Stop condition 
   SD A   
   SCL...

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2.2. Master mode 
Master mode generates the start condition on the I2C bus and outputs clocks to the I2C bus. 
When the MSS bit in the IBCR register is set to 1 while the I2C bus is in idle state 
(SCL=HIGH, SDA=HIGH), master mode is activat ed, causing the ACT bit in the IBCR register 
to be set to 1. 
 Generating start condition 
The start condition is generated under the following condition. 
   When SDA=H, SCL=H, ISMK :EN=1 and IBSR:BB=0, the IBCR:MSS bit is set to 1....

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 In operation mode 4 (I
2C mode), the bus clock is used at a frequency no lower than 8 MHz. Also note that 
setting of a baud rate generator that exceeds 400 kbps is prohibited.   
 
 Slave address output 
Outputting the start condition causes data that are set  in the TDR register to be output as the address, 
starting with bit 7. When FIFO is enabled, the datum in  the TDR register that is written the earliest is output. 
Bit 0 is used as the data direction bit (R/W)....

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Figure 2-6 Address and data direction (when transmit/receive FIFO is enabled) 
                             1        2      3       4       5       6       7       8 
SCL  
SDA  A6( D7)  A5( D6)  A4(D5)   A3( D4)  A2(D3)   A1(D2)   A0(D1)  R/W( D0)  ACK 
 
BB bit 
 
MSS bit  ( *1)  
 
INT bit (*2) 
 
 
R SA b i t  
 
RDRF bi t 
 
INT bit 
 
A6 to A0: Address bits 
D 7 t o  D0 :  T D R r e gi s t e r  bi t s  
R/W: Data di recti on (writ ing i f L) 
ACK: Acknowl edge...