Fujitsu Series 3 Manual

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
Figure 2-3 ORE (Overrun Error) flag bit set timing 
 
Receive data
RDRF
ORE
SP
Precautions: If the next data is transferred before the receive data is read (RDRF=1), an overrun error occurs. ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7
  
 

 LIN break field detection  flag (LBD) set timing 
If 0 is input for a width of 11 bits or more as Serial Input (SIN), the LBD bit is set to 1. If LIN break 
field interrupts are enabled (ESCR:LBIE  = 1) then,...

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
2.2.  Interrupt and flag set timi ng when receive FIFO is used 
If receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE 
register (FBYTE)) is received. 
 Interrupt and flag set timing  when receive FIFO is used   
If the receive FIFO is used, an interrupt occurs depending on the value set for the FBYTE register.   
  When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Se rial Status register is 
set to...

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
Figure 2-6 ORE (Overrun Error) flag bit set timing 
 
Receive data
FIFOBYTE 
(Receive)
RDRF
62th byte
62
Precautions:
If the FIFO capacity is displayed by the FBYTE and if the next data is received, an overrun error occurs.
This figure shows that the 64 bytes of FIFO capacity are used.
63th byte   64th byte 65th byte
STSPST SP ST  SP ST SP ST66th byteSP
61                        Valid byte display
ORE
An overrun error occurred.
62                        63...

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
2.3.  Transmit interrupt and flag set timing 
A transmit interrupt occurs when outgoing data is transferred from the Transmit Data Register 
(TDR) to the transmit shift register (SSR:TDRE = 1) and transmission starts and when no 
transmission is performed (SSR:TBI = 1).   
  Transmit interrupt and flag set timing 
  Transmit data empty flag (TDRE) set timing 
After data has been transferred from the Transmit Data  Register (TDR) to the transmit shift...

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
2.4.  Interrupt and flag set timi ng when transmit FIFO is used 
When the transmit FIFO is used, an interrupt occurs if the FIFO contains no data. 
 Transmit interrupt and flag set ti ming when transmit FIFO is used 
  If the transmit FIFO contains no data, the FIFO tran smit data request bit (FCR1:FDRQ) is set to 1. 
If FIFO transmit interrupts are enabled (FCR1:FTIE=1), a transmit interrupt occurs. 
   If a transmit interrupt has occurred and you have...

 
3. Dedicated Baud Rate Generator 
 
3.  Dedicated Baud Rate Generator 
For the LIN interface (ver. 2.1) transmitting/receiving clock source, either of the following can 
be selected. 
- Dedicated baud rate generator (reload counter) 
- An external clock input to the baud rate generator (reload counter) 
  LIN interface (ver. 2.1) baud rate 
Select one of the following two baud rates. 
  Baud rate obtained by dividing an internal clock using the dedicated baud 
rate generator (reload counter) 
This...

 
3. Dedicated Baud Rate Generator 
 
3.1.  Baud rate settings 
The following explains how to set the baud rate, and also a result of serial clock frequency 
calculation. 
  Calculating the baud rate 
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). 
The baud rate is obtained in the following formulas. 
(1) Reload value 
 
(2) Calculation example 
To set the 16 MHz bus clock, to use the internal clock, and to set the 19200-bps baud rate, set the reload...

 
3. Dedicated Baud Rate Generator 
 
  Reload value and baud rate for each bus clock frequency 
Table 3-1 Reload values and baud rates 
8 MHz  10 MHz  16 MHz 20 MHz  24 MHz  32MHz Baud rate 
(bps) 
Value ERRValue ERR ValueERRValueERRValueERR Value ERR
8M  - - - -  - - -  - - - - 0 
6M  - - - -  - - -  - - - - - 
5M  - - - -  - - -  - - - - - 
4M  - - -  - -  - 4 0  5 0 7 0 
2.5M  - - 3  0  - - -  - - - - - 
2M  3 0 4  0 7 0 9  0 11  0 15  0 
1M  7 0 9  0 15 0 19  0 23 0 31 0 
500000  15 0 19 0  31 0 39...

 
3. Dedicated Baud Rate Generator 
 
  Allowable baud rate range for data reception 
The following shows the ra nge of baud rate error allowed fo r the destination to receive data. 
Set the reception baud rate error by using the following  formulas to ensure that the value falls within the 
allowable range. 
Figure 3-1 Allowable baud rate range for data reception 
FUJITSU SEMICONDUCTOR LIMITED 
 
LIN
trans fer rate
 Start 
Sampling  
    
Allowable 
minimum 
transfer rate  
FL
Single data frame...

 
3. Dedicated Baud Rate Generator 
 
From the above formulas that yields the minimum/maximum baud rates, the allowable baud rate errors 
between the LIN interface (ver. 2.1) an d the destination can be obtained as shown in the following table. 
Reload value (V)Maximum allowable baud rate error Minimum allowable baud rate error
3 0%  0 
10 +3.28% -3.41% 
50 +4.83% -4.87% 
100 +5.04% -5.07% 
200 +5.15% -5.16% 
32767 +5.26% -5.26% 
 
 
Receive accura cy 

depends on the number of bits per fra me, bus...