Fujitsu Series 3 Manual

 
6. LIN Interface (ver. 2.1) Registers 
 
6.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set an operation mode, to select a transmission 
direction, data length, and stop bit length, and enable or disable an output of serial data to 
their pins. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSBL - - SOE 
Attribute     R/W R/W R/W  R/W R/W - - R/W 
Initial 
value     0 0 0 0 0 - 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation mode setting bits  These bits set an...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 3] SBL: Stop bit length select bit 
This bit sets a stop bit length (the frame end mark of the transmit data). 
If SBL=0 and ESCR:ESBL=0 are set: One (1) stop bit is set. 
If SBL=1 and ESCR:ESBL=0 are se t: Two (2) stop bits are set. 
If SBL=0 and ESCR:ESBL=1 are se t: Three (3) stop bits are set. 
If SBL=1 and ESCR:ESBL=1 are se t: Four (4) stop bits are set. 
Bit Description 
ESCR.ESBL=0 1  bit 0 
ESCR.ESBL=1 3 bits 
ESCR.ESBL=0 2  bits 1 
ESCR.ESBL=1 4...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the Receive Error flag, detect an LIN Break field, and clear the Receive Error flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - LBD FRE ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - R/W  R R  R R R    
Initial 
value  0 - 0 0 0 0 1 1    
 
[bit 15] REC: Receive Error flag clear bit  This bit clears the FRE and ORE flags of  the...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 13] LBD: LIN Break field detection flag bit 
This bit shows a detection of LIN Break field. 
When 11-bit wide or more of serial input (SIN) are LOW , the LBD bit is set to 1. If the LIN Break field 
interrupt enable bit (LBIE) is 1 during this time, a status interrupt occurs. 
When read: 
If this bit is 1: An LIN Break field has been detected. 
If this bit is 0: An LIN Break field has not been detected. 
When written: 
If this bit is set to 0: The LBD bit...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] ORE: Overrun error flag bit 
  If an overrun occurs during data receptio n, this bit is set to 1. If the REC bit of Serial Status Register 
(SSR) is set to 1, this flag is cleared. 
   If the ORE and RIE bits are 1, a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 8] TBI: Transmit bus idle flag bit 
  This bit indicates that the LIN interface (ver. 2.1) is not transmitting data. 
   When transmit data is written in the Transmit Data Register (TDR), this bit is set to 0. 
   When the LIN Break field is set (SMR :LBR=1), this bit is set to 0. 
   If the Transmit Data register (TDR) is empty (TDRE=1) an d if no transmission is started, this bit is set to 
1. 
   If the Transmit Data Register is emptied after the...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to enable/disable an LIN 
Break field interrupt, detect an LIN Break field, set an LIN Break field length and a Break 
delimiter length, and select a stop bit length. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) - ESBL- LBIE LBL1LBL0 DEL1 DEL0
Attribute      -  R/W  - R/W R/W R/W  R/W R/W 
Initial 
value     0 0 - 0 0 0 0 0 
 
[bit 7] Reserved bit...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 4] LBIE: LIN Break field detect interrupt enable bit 
This bit enables or disables an LIN Break field detect interrupt. 
If the LIN Break field detect flag (LBD) is 1, a r eceive interrupt occurs when an interrupt is enabled 
(LBIE=1). 
Bit Description 
0  Disables an LIN Break field detect interrupt. 
1  Enables an LIN Break field detect interrupt. 
 
[bit 3:2] LBL1/0: LIN Break field length se lect bits (valid in master mode only) 
   These bits set an...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.5.  Receive Data Register/Transmit Data Register 
(RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data  is read from it. This register functions as 
the Transmit Data Register when data is written in it. 
  Receive Data Register (RDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        R R  R R R  R R R 
Initial 
value      0 0 0 0 0...

 
6. LIN Interface (ver. 2.1) Registers 
 
  Transmit Data Register (TDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        W W  W W W  W W W 
Initial 
value      1 1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a data bu ffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to the transmit shift register. Then, the data...