Fujitsu Series 3 Manual

 
6. LIN Interface (ver. 2.1) Registers 
 
6.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and 
BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. Also, an external clock can be selected as the clock source of 
the reload counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field EXT (BGR1) (BGR0) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
   The Baud...

 
6. LIN Interface (ver. 2.1) Registers 
 
 
  Data must be written in the Baud Rate Generato r Registers (BGR1 and BG
 R0) in 16-bit data access 
mode. 
   If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are 
reloaded only after the counter value has reached 15h00. In order to validate the new set values 
immediately, change the BGR1/0 set values  and execute the programmable clear (UPCL). 
   If the reload value is even, the LOW signal width of  serial...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select transmit or receive 
FIFO, enable transmit FIFO interrupt, and control the interrupt flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They must always be set...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] FRIIE: Receive FIFO idle detect enable bit 
This bit sets to detect the receive id le state if receive FIFO contains valid data for more than 8-bit hours. If 
the receive interrupt is enabled (SCR:RIE=1), a receive interrupt is genera ted when the receive idle state is 
detected. 
If set to 0: The receive idle  state detection is disabled. 
If set to 1: The receive idle state detection is enabled. 
Bit Description 
0  Disables the receive FIFO idle...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is  set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO select bit  This bit selects the tr ansmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO1, and receive FIFO is assigned FIFO2. 
If set to 1, transmit FIFO...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.8.  FIFO Control Register 0 (FCR0) 
FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      - R R/W  W R/W  R/W  R/W R/W 
Initial 
value     - 0 0 0 0 0 0 0 
 
[bit 7] Unused bit  This bit value is undefined when read. 
This bit has no effect when written. 
 
[bit 6] FLST: FIFO...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If th is 

bit is 1, data is being reloaded in the read  poin
 ter. Therefore, data writing except for FIFO...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 3] FCL2: FIFO2 reset bit 
This bit resets the FIFO2 value. 
If this bit is set to 1, the FIFO2 internal state is initialized. 
Only the FCR1:FLST2 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit  During writing During reading 
0 No  effect. 
1 FIFO2 is reset.  0 is always read. 
 
 
  Disable th e tra

nsmission and receptio n first, and then reset FIFO2. 
   Set th e tran

smit FIFO interrupt enable bit to 0 before...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 1] FE2: FIFO2 operation enable bit 
This bit enables or disables the FIFO2 operation. 
  To use the FIFO2 operation,  set this bit to 1. 
   If FIFO2 is set as transmit FIFO and if data exists in FIFO2 when this bit is set to 1, the data 
transmission starts immediately when  the LIN interface (ver. 2.1) is enabled to transmit data (TXE=1). 
During this time, set both TIE and TBIE bits to 0. Then, set this bit to 1 and set both TIE and TBIE 
bits to 1. 
...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when a certain number of data sets is 
received in the receive FIFO. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register...