Fujitsu Series 3 Manual

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.8.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Reserved bit  0 is always read during reading. 
0 must always be written during writing. 
 
[bit...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If th is 

bit is 1, data is being reloaded in the read  poin
 ter. Therefore, data writing except for...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
 
  Disable the transmission and receptio n first, and then reset FIFO2. 
   Set the tran

smit FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE2 register is set to 0. 
 
[bit 2] FCL1: FIFO1 reset bit  This bit resets th e FIFO1 state. 
Wh

en this bit is set to 1, the FIFO1 internal state is initialized. 
Only the FCR1:FLST1 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 0] FE1: FIFO1 operation enable bit 
This bit enables or disables the FIFO1 operation. 
  To use the FIFO1 operation,  set this bit to 1. 
   If FIFO1 is set as transmit FIFO (FCR1:FSEL=0) and if  data exists in FIFO1 when this bit is set to 1, 
the data transmission starts immediately when th e UART is enabled to transmit data (SCR:TXE=1). 
During this time, set both SCR:TIE bit and SCR:TBIE bit to 0. Then, set this bit to 1 and set both 
TIE...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. 
 
Bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the effective data coun t of FIFO. The following shows the settings of the 
FCR1:FSEL bit. 
Table 5-3 Display of...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
Chapter: CSIO (Clock Sync Serial Interface) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  59  
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writing Sets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets  already written in FIFO but not transmitted yet 
During reception: The number of  data...

 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
This chapter explains the LIN communication function, a part of multifunctional serial interface 
functions and supported in Operation Mode 3. 
 
1.
 Overview of LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
2. LIN Interface (Ver.  2.1) Interrupts 
3. Dedicated Baud Rate Generator 
4. LIN Interface (Ver. 2.1) Operations 
5. Operation Mode 3 (LIN Communication Mode)...

 FUJITSU SEMICONDUCTOR LIMITED 
1.  Overview of LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
The LIN interface (ver. 2.1) (LIN communication control interface ver. 2.1) supports functions 
complying with the LIN bus. It also has transmit/receive FIFO (up to 128 × 9 bits each)*1 
installed. 
 Functions of LIN interface (ver. 2.1) (L IN communication control interface ver. 
2.1) 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
...

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
2.  LIN Interface (Ver. 2.1) Interrupts 
Receive interrupts and transmit interrupts are provided for LIN interface (ver. 2.1). These 
interrupt requests can be generated if: 
- Incoming data is set in the Receive Data Register (RDR) or a data receive error occurs. 
- Outgoing data is transferred from the Transmit Data Register (TDR) to the transmit shift 
register and the data transmission is started. 
- The transmit bus is idle (No data transmission occurs)....

 
2. LIN Interface (Ver. 2.1) Interrupts 
 
2.1.  Receive interrupt and flag set timing 
Data reception can be interrupted by a receive completion (SSR:RDRF), a receive error 
occurrence (SSR:ORE, FRE), or a LIN break field detection. 
  Receive interrupt and flag set timing   
Upon detection of the first  stop bit, received data are stored in the Receive Data Register (RDR). When the 
data reception is completed (SSR:RDRF = 1) or when  a data receive error occurs (SSR:ORE, FRE = 1), 
each flag is set....