Fujitsu Series 3 Manual

 
4. Dedicated baud rate generator 
 
4.2.  CSIO (Clock Sync Serial Interface) setup procedure 
and program flow 
The CSIO (Clock Sync Serial Interface) allows bidirectional and synchronous serial data 
transmission. 
 CPU-to-CPU connection 
Select the bidirectional communication for the CSIO (C lock Sync Serial Interface). Connect two CPUs to 
each other as shown in Figure 4-1 . 
Figure 4-1 A connection example for CSIO (Clock Sync Serial Interface) bidirectional communication 
 
CPU_1 (Master)CPU_2...

 
4. Dedicated baud rate generator 
 
  If FIFO is used 
Figure 4-3 An example of bidirectional communication flowchart (if FIFO is used) 
 
(Master system)
Start
Set an operation 
format.
Set N bytes in the 
transmit FIFO buffer, 
and set FDRQ bit to 
0.
RDRF=1
(Slave system)
Send data. Start
RDRF=1
Yes
Yes
No No
Send data.
(ANS)
Enable the transmit/ receive FIFO.
Read and process 
the FBYTE data.
Read and process 
the FIFOBYTE data.
Set N bytes in the 
transmit FIFO buffer, 
and set FDRQ bit to 
0....

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.  CSIO (Clock Sync Serial Interface) registers 
This section provides a list of CSIO (Clock Sync Serial Interface) registers. 
  CSIO (Clock Sync Serial  Interface) register list 
 
Table 5-1 CSIO (Clock Sync Serial Interface) register list 
  bit 15                           bit 8 bit 7                            bit 0
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) is used to  enable/disable a transmit/receive interrupt, 
enable/disable a transmit idle interrupt, and enable/disable data transmission and reception. 
Also, the register can set the SPI connection and reset the CSIO settings. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL MS SPI RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W    
Initial 
value  0 0 0 0 0...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 14] MS: Master/Slave function select bit 
Selects the master or slave mode. 
  If set to 0: The master mode is selected. 
   If set to 1: The slave mode is selected. 
 
Bit Description 
0 Master  mode 
1 Slave mode 
 
 
  If th e sla

ve mode is selected and if SMR:SCKE =0, the extern
 al clock is entered directly. 
   After you have set the MS bit, enable data reception (RXE=1). 
 
[bit 13] SPI: SPI corresponding bit  This bit allows th e SPI...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 10] TBIE: Transmit bus idle interrupt enable bit 
  This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. 
   If the TBIE bit and SSR:TBI bit are 1, a tr ansmit bus idle interrupt request is output. 
 
Bit Description 
0  Disables the transmit bus idle interrupt. 
1  Enables the transmit bus idle interrupt. 
 
[bit 9] RXE: Data receive enable bit  Enables or disables a CSIO data reception. 
  If set to 0:...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to select an operation mode, to set a transmission 
direction, data length and serial clock inversion, and to enable or disable an output of serial 
data and clock to their pins. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSCINVBDS SCKE SOE 
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 3] SCINV: Serial clock invert bit 
Inverts the serial clock format. 
If set to 0: 
  The signal detect level of serial clock output is set to HIGH. 
   The transmit data is output at a falling edge of serial clock during normal transfer, but it is output in 
synchronization with a rising edge of serial clock during SPI transfer. 
   The receive data is sampled at a rising edge of serial clock during normal transfer, but it is sampled at a...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 1] SCKE: Master mode serial clock output enable bit 
This bit controls the serial clock I/O port. 
Bit Description 
0  Disables a serial clock output. 
1  Enables a serial clock output. 
 
 
If this 

bit is used as the SCK pi n, the GPIO must also be se
 t. 
 
[bit 0] SOE: Serial data output enable bit  This bit enab les or 

disables a serial data output. 
Bit Description 
0  Disables a serial data output. 
1  Enables a serial data output....

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the Receive Error flag, and clears the Receive Error flag. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - - - ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - -  - R R  R R    
Initial 
value  0 - - - 0 0 1 1    
 
[bit 15] REC: Receive error flag clear bit  This bit clears the ORE flag of th e Serial Status Register (SSR)....