Fujitsu Series 3 Manual

    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   6 
 Explanation of Block Diagram  
  DMAC  
DMAC is in 8 -ch configuration. Each channel performs independent transfer. The priority controller 
controls the transfer  operations of these channels, when there is a conflict among them.  
 Connection to the system  
The diagram of the system configuration in the figure has been simplified for explanation purposes. For 
more details, see the...

    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   7 
2.2.  I/O Signals of DMAC 
This section describes the I/O signals of DMAC. 
 Transfer Request Signals to be Input to DMAC  
Table 2-1 shows a list of the transfer request signals to be input to DMAC and the interrupt signals from the 
corresponding Peripherals.  
Table 2-1 List of Transfer Request Signals and Interrupt Signals from Corresponding Peripherals  
IDREQ No. Interrupt Signal of...

    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   8 
 Interrupt Signals Output from DMAC  
Table 2-2 shows a list of the interrupt signals output from DMAC.  
Table 2-2 List of Interrupt Signals from DMAC  
Name of 
Interrupt Signal 
Interrupt Factor 
Register 
Interrupt Enable 
Register Interrupt Type 
DIRQ0  DMACB0.SS[2:0]  DMACB0.CI ch.0 successful transfer completion interrupt 
DMACB0.EI ch.0 unsuccessful transfer completion interrupt...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   9 
3. Functions and Operations of DMAC  
This chapter describes the operations of D MAC in each transfer mode. 
 
3.1 Software -Block Transfer  
3.2  Software -Burst Transfer  
3.3  Hard ware-Demand Transfer  
3.4  Hardware- Block Transfer & Burst Transfer  
3.5  Channel Priority Control  
 
CHAPTER  8: DMAC 
MN706-00002-1v0-E 
188 
MB9Axxx/MB9Bxxx  Series  

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   10 
3.1.  Software- Block Transfer  
This section describes Software -Block transfer.  
Figure 3-1 shows an example of the operation of Software -Block transfer. In this example, the following 
settings apply.  
⋅   Transfer mode  : Software request Block transfer (ST=1, IS=000000, MS=00)  
⋅   Transfer sour ce start address   : SA(DMACSA=SA)  
⋅   Transfer source address control...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   11 
DMAC performs the following operation, when the transfer content is set from CPU and then the start of 
the transfer is instructed.  
⋅   Due to the specification of the transfer data width, each transfer is performed by half -word (16bit) . 
⋅   According to the start addresses of the transfer source and transfer destination, the data width and the 
incremented/fixed...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   12 
3.2.  Software -Burst Transfer  
This section describes Software- Burst transfer. 
Figure 3-2 shows an example of the operatio n of Software -Burst  transfer. In this example, the following 
settings apply.  
⋅   Transfer mode  : Software request B urst transfer  (ST=1, IS=000000,  MS=01)  
⋅   Transfer source start address   : SA(DMACSA=SA)  
⋅   Transfer source address   :...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   13 
3.3.  Hardware-Demand Transfer  
This section describes Hardware-Demand transfer. 
Hardware-Demand transfer is used when performing DMA transfer by the transfer request signal from the 
Peripherals  of  USB, MSF  and ADC . 
Hardware- Demand transfer is a method used to receive the transfer request signal from Peripherals on a 
signal level. If the transfer request signal is on...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   14 
3.4.  Hardware-Block Transfer & Burst Transfer 
This section describes Hardware- Block transfer and Burst transfer. 
Hardware-Block transfer or Hardware -Burst transfer is used when performing DMA transfer by the transfer 
reques t signal from the Peripheral of the base timer or external interrupt.  
Hardware- Block transfer and Hardware- Burst transfer are methods used to...

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   15 
Figure  3-5 shows an example of the oper ation of Hardware-Burst transfer.. In this example, the following 
settings apply. The settings of the addresses of the transfer source and transfer destination as well as the 
transfer data width are omitted.  
⋅   Transfer mode  :  Hardware-Burst transfer   
   (ST=0 , IS= Peripheral at the transfer request source,  MS=01) 
⋅...