Fujitsu Series 3 Manual

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   46 
5.4.  Configuration B Register  (DMACB) 
This section describes configuration B register ( DMACB). 
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field - MS[1:0] TW[1:0] FS FD RC RS RD EI CI SS[2:0] 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field - - - - - - -...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   47 
[bit24] FD : Fixed Destination  
This bit specifies whether to increment or fix the transfer destination address.  
bit24 Function 
0 Increments the transfer destination address according to TW. (Initial value) 
1 Fixes the transfer destination address. 
 
[bit23] RC : Reload Count (BC/TC reload)  
This bit controls the reload function of BC and TC.  
When this bit is set to "1" , the...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   48 
[bit20] EI :Error Interrupt (unsuccessful transfer completion interrupt enable)  
This bit enables or disables the notification of an interrupt when a transfer has been unsuccessfully 
completed.  
When this bit is set to  "1", an interrupt is issued if SS is in the following status upon completion of the 
transfer.  
⋅   Address overflow  
⋅   Stop by transfer stop request from a...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   49 
If various errors occur simultaneously, the termination code is indicated according to the following priority.  
Highest 
priority  
 
Reset 
Clearing by writing "000" 
Address overflow 
Stop request 
Transfer source access error 
Transfer destination access error  
Lowest 
priority  
 
[bit15: 8] Reserved  
When writing, always write " 0". "0" is always read....

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   50 
5.5.  Transfer Source Address Register ( DMACSA) 
This section describes transfer source address register  (DMACSA ). 
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field DMACSA[31:16] 
Attribute R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field DMACSA[15:0] 
Attribute R/W 
Initial 
Va l u e 0  0  0  0  0  0  0...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   51 
5.6.  Transfer Destination Address Register  (DMACDA ) 
This section describes  transfer destination address register ( DMACDA). 
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field DMACDA[31:16] 
Attribute R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field DMACDA[15:0] 
Attribute R/W 
Initial 
Va l u e 0  0  0  0...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   52 
5.7.  Notes on Register Setting  
Care must be taken on the following matters when setting the DMAC registers.  
⋅  The  DMACR, DMACA, DMACB, DMACSA  and  DMACDA  registers can be accessed by byte, 
half -word and word.  
⋅   The register address in DMAC cannot be set to the DMACSA  or  DMACDA  register.  
⋅   Channel setting registers cannot be changed during DMA transfer, except the DE/DH...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
232 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
CHAPTER: I/O PORT 
This chapter explains the I/O port. 
 
1.
 Overview 
2. Configuration, Block Diagram, and Operation 
3. Setup Procedure Example 
4. Register List 
5. Usage Precautions 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFGPIO-E02.3 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  9: I/O  PORT 
MN706-00002-1v0-E 
233 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
This section provides an overview of the I/O port. 
The I/O port of this series provides the following features. 
  The I/O port of this series shares the following functions. 
   GPIO 
General-purpose I/O ports, which can read an inpu t level and set an output level from the CPU. 
   Peripheral input/output 
Digital input/output signal ports of peripheral functions. 
   Special I/O ports 
   Analog input port 
An analog input port of an A/D converter. 
   USB port 
...