Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
4.1.  Enable Interrupt Request Register [ENIR] 
The ENIR is used to control masking an external interrupt request output. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field EN15 EN14 EN13 EN12 EN11 EN10 EN9EN8EN7EN6EN5EN4EN3 EN2 EN1EN0
Attribute R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Register functions 
[bit15:0] EN15 to EN0: External interrupt enable bit 
Bits EN15 to EN0...

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4.2.  External Interrupt Request Register [EIRR] 
The EIRR indicates that an external interrupt request is detected. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field ER15 ER14 ER13 ER12 ER11 ER10 ER9ER8ER7ER6ER5ER4ER3 ER2 ER1ER0
Attribute R R R R R R  R R R R R R  R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
 
  Register functions 
[bit15:0] ER15 to ER0: External interrupt request detection bit 
Bits ER15 to ER0 correspond to pins...

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4.3.  External Interrupt Clear Register [EICL] 
The EICL is used to clear the held interrupt cause. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field  ECL 
15  ECL 
14  ECL
13 ECL 
12  ECL 
11  ECL
10 ECL
9  ECL
8  ECL
7  ECL
6  ECL
5  ECL
4  ECL 
3  ECL 
2  ECL
1  ECL
0 
Attribute  R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 
 
  Register functions 
[bit15:0] ECL15 to ECL0: Exter nal...

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4.4.  External Interrupt Level Register [ELVR] 
The ELVR is used to select the level or edge of the signal detected as an external interrupt 
request. 
 Register configuration 
 
bit 31 30 2928 27 2625242322212019 18 17 16
Field LB15 LA15 LB14 LA14 LB13 LA13LB12LA12LB11LA11LB10LA10LB9 LA9 LB8LA8
Attribute  R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field LB7 LA7...

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4.5.  Non Maskable Interrupt Request Register [NMIRR] 
The NMIRR Register indicates that a non maskable interrupt (NMI) request is detected. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved NR0
Attribute -  R 
Initial 
value  - 0 
 
  Register functions 
[bit15:1] Reserved: Reserved bits 
Bits 7 to 1 are indefinite in read mode. 
They have no effect in write mode. 
[bit0] NR: NMI request detection bit  The NR bit corresponds to pin NMIX....

 
4. Registers 
 
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Chapter: External Interrupt and NMI Control Sections 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  17 
4.6.  Non Maskable Interrupt Clear Register [NMICL] 
The NMICL Register is used to clear the held interrupt cause. 
  Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved NCL0
Attribute -  R/W
Initial 
value  - 1 
 
  Register functions 
[bit15:1] Reserved: Reserved bits 
Bits 7 to 1 are indefinite in read mode. 
They have no effect...

    1. Overview of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHA PTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   2 
CHAPTER: DMAC 
This chapter describes DMAC.  
 
1.
 Overview of DMAC 
2. Configuration of DMAC 
3. Functions and Operations of DMAC 
4. DMAC Control 
5. Registers of DMAC 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFDMAC -E01. 2_MHDMAC -E01.0 
CHAPTER  8: DMAC 
MN706-00002-1v0-E 
181 
MB9Axxx/MB9Bxxx  Series  

    1. Overview of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   3 
1. Overview of DMAC   
DMAC (Direct  Memory Access  Controller)  is a  function block that transfers data  at high speed  
without CPU.  Using DMAC improves the system performance.  
 Overview of DMAC  
⋅  DMAC has its own bus which is independent from the CPU bus; therefore, it allows for transfer 
operati on even when the CPU bus is accessed.  
⋅   It consists of 8 channels enabled to...

    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   4 
2. Configuration of DMAC  
This chapter describes the system configuration of DMAC and the I/O pins of DMAC.  
 
2.1 DMAC and System Configuration  
2.2  I/O Signals of DMAC  
 
CHAPTER  8: DMAC 
MN706-00002-1v0-E 
183 
MB9Axxx/MB9Bxxx  Series  

    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   5 
2.1. DMAC and System Configuration 
This section describes DMAC and its system configuration.  
 Block Diagram  
Figure 2-1 shows a diagram of DMAC and its system configuration.  
Figure 2-1 Block Diagram of DMAC and System Configuration  
 
DMAC and System block diagram 
DRQSEL
IDREQ[31:0]
DMAC
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
Channel priority control
DMAC system bus (AHB/Peripheral)...