Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
Chapter: External Interrupt and NMI Control Sections 
This chapter explains the functions and operations of the external interrupt and NMI control 
sections. 
 
1. Overview 
2. Block Diagram 
3. Operations and Setting Procedure Examples 
4. Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CODE: 9BFEXTINT-E02.1_FW12-J1.03 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
MN706-00002-1v0-E 
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MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
1. Overview 
The external interrupt and NMI control sections have the following features. 
  Has up to 16 external interrupt input pins and one NMI input pin mounted. 
   Possible to select the H level, L level, rising ed ge, or falling edge to detect an external interrupt. 
   Possible to use an external interrupt input or NMI input to return from standby mode. 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
MN706-00002-1v0-E 
166 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
2. Block Diagram 
The following shows the block diagram of the external interrupt and NMI control sections. 
Figure 2-1 Block diagram of external interrupt and NMI control sections 
Level detectionNormal: Falling edgeStop release: L levelCause F/F
NMIRRNon Maskable Interrupt Cause Request 
Register
NMICLNon Maskable Interrupt Cause Clear 
Register
NMIIRQ
NMIX
Level 
detectionCause F/FEN gate
EIRR
External Interrupt Cause Register
ENIR
Enable Interrupt Request Register...

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3.  Operations and Setting Procedure Examples 
This section explains operations and setting procedure examples. 
 
3.1 Operations of external interrupt control section  
3.2  Operations of NMI control section 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
MN706-00002-1v0-E 
168 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
3.1.  Operations of external interrupt control section 
 Overview of operations in ext ernal interrupt control section 
The external interrupt control section outputs an extern al interrupt request to the interrupt controller in the 
following procedure. 
1.  The signal input to pin INTxx detects the edge or leve l specified in the External Interrupt Level Register 
(ELVR). The edge or level to be detected can be selected from the following four types: 
H level, L level,...

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 Canceling an external interrupt request 
When the external interrupt detection condition is set to  the H or L level, an interrupt cause is held in 
the External Interrupt Request Register (EIRR) even  if an external interrupt request input (INTxx) is 
canceled. Therefore, an exte rnal interrupt request (INTIRQxx) remains output to the interrupt controller. 
Execute the following steps to cancel  an external interrupt request. 
1.  Read the External Interrupt Request...

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3.2.  Operations of NMI control section 
 Overview of NMI control section 
The NMI control section outputs an NMI interrupt reque st (NMIIRQ) to the CPU if the edge or level is 
detected from the signal input to the NMI input pin (NMIX). The following edge or level is detected. 
   Normal mode  :  Falling edge 
   Stop mode  :  L level 
 Canceling an NMI request 
To cancel an NMI request, clear the  request register in the same way as for an external interrupt request....

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3.3.  Returning from timer or stop mode 
 Overview 
An external interrupt and NMI requests can be used to return from timer or stop mode. 
In timer or stop mode, the signal first input to pin INTxx or NMIX is input asynchronously, and the device 
can return from timer or stop mode. 
  Setting before changing to stop mode 
To use an external interrupt request, in the Enable In terrupt Request Register (ENIR), specify the pin used 
to return from stop mode and also specify...

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 Notes on returning from stop mode 
Any other external interrupt requests cannot be recognized until the oscillation stabilization wait time lapses 
after stop mode was released. 
(For INT01 in Figure 3-5 , any external interrupt requests cannot be recognized.) 
Th erefore, to i
n

put an external interrupt after stop mode  was released, input an external interrupt signal after 
the oscillation stabilization wait time lapsed. 
Figure 3-5 Returning from stop mode 
STOP...

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4. Registers 
This section provides a list of registers. 
 Register list 
The following shows a list of registers in the  external interrupt and NMI control sections. 
Table 4-1 Registers in external interrupt and NMI control sections 
Abbreviation Register name See 
ENIR  Enable Interrupt Request Register  4.1 
EIRR External Interrupt Request Register  4.2 
EICL External Interrupt Clear Register  4.3 
ELVR External Interrupt Level Register    4.4 
NMIRR Non Maskable...