Fujitsu Series 3 Manual

    3. Functions and Operations of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   16 
3.5.  Channel Priority Control  
This section describes the  channel priority control. 
 Channel Priority Control  
If multiple channels have transfer requests, DMAC switches the channel subject to the transfer among them 
at the timing of the Transfer Gap of each channel. At this point, the next channel to which the tr ansfer will 
be performed is determined according to the...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   17 
4.  DMAC Control  
This chapter describes DMAC control methods in details.  
 
4.1 Overview of DMAC Control  
4.2  DMAC Operation and Control Procedure for Software Transfer  
4.3  DMAC Operation and Control Procedure for Hard ware (EM=0) Transfer  
4.4  DMAC Operation and Control Procedure for Hardware (EM=1 ) Transfer 
 
CHAPTER  8: DMAC 
MN706-00002-1v0-E 
196 
MB9Axxx/MB9Bxxx  Series  

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   18 
4.1.  Overview of DMAC Control  
This section provides an overview of DMAC control.  
The control register of each channel of DMAC has EB (individual -channel operation enable bit) and PB 
(individual -channel pause bit). By manip ulating these bits, the start of DMA transfer operation (operation 
enabled), the forced termination of transfer operation (operation disabled) and the pause of transfer...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   19 
4.2.  DMAC Operation and Control Procedure for Software 
Transfer 
This section describes DMAC operation and control procedure for software transfer.  
Figure 4-1 Transitional Diagram of Software Transfer State  
 
Software DMA operationTransition by CPU
Transition by DMAC
      2        4,5
    3
Disable
DE
=0  or EB =0 or
DH !=0000  or PB=1
initial : SS=000
after stop :SS=code
Transfer
DE =1...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   20 
 Description of Each State 
Disable state  
In this state, the transfer of the channel to be controlled is prohibited. Channels in this state do nothing 
and wait for instruction from CPU. At the system reset, DE=0,  EB=0,  DH=0000  and  PB=0  apply to this 
Disable state.  
Transfer state  
In this state, the transfer of the channel to be controlled is enabled. Channels in this state perform...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   21 
Figure  4-2 Example of Operation of Software- Block Transfer 
 
DMA status Transfer 
Example of Block transfer mode (software DMA operation)
start / normal end / error stop / force stop
Transfer action
 Disable 
Example 1 :normal end
 Disable 
TC(no reload)
3210
SS
000101 ( normal end)
Start request  from CPUTransfer normal end
BC
 Transfer 
Example 2 : error stop
 Disable 
32
000011 
(Source...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   22 
6. Transfer state, Pause state =>  Disable state / Forced transfer stop  
If an instruction to disable i ndividual-channel operation or an instruction to disable all- channel operation 
is issued from CPU to a channel in Transfer state or Pause state, the transfer operation of that channel 
can be forced to stop (for the operation when an instruction to disable operation is issued to a channel in...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   23 
Even if instructed from CPU, the transfer may not be put on pause , and instead, it may be successfully 
completed due  to factors such as transfer mode (Burst/Block/Demand) and transfer status (the number 
of transfers performed, the timing of instruction to put  the operation  on pause ). Also, if a transfer error 
occurs before the transfer stops, error stop  applies to the transfer . 
Figure...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   24 
Figure  4-3 shows an example of the case where an instruction to put all -channel operation on pause. The 
explanation of the figure is as follows.  
At the beginning, three channels, namely ch.0, ch.1  and  ch.2 , perform their transfer operations in Block 
transfer mode. ch.2 successfully completes its transfer, moves to Disable state and sets SS=101. Then, 
ch.0 and ch.1 perform transfers...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   25 
A certain channel is performing transfer operation. CPU issues an instruction to put in dividual-channel 
operation on pause to that channel. The instruction is issued after the transfer is completed and it moves to 
Disable state (DE=1, DH=0000, EB=0, PB=0) . This phenomenon can occur, because the channel currently 
performing transfer operation  changes its state outside CPU ’s intention. In...