Fujitsu Series 3 Manual

 
4. Registers 
 
4.17.  IRQ31 Batch Read Register (IRQ31MON) 
IRQ31MON indicates all of the interrupt requests allocated to interrupt vector no. 47. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field BTINT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:16] Reserved: Reserved bits  Reads out 0. 
 
[bit15:0] BTINT: 
bit no.  bit  Description 
0 No IRQ1 interrupt request on the base...

 
4. Registers 
 
bit no.  bit Description 
0 No IRQ0 interrupt request on the base timer ch. 2 4 
1 IRQ0 interrupt request on the base timer ch. 2 
0 No IRQ1 interrupt request on the base timer ch. 1 3 
1 IRQ1 interrupt request on the base timer ch. 1 
0 No IRQ0 interrupt request on the base timer ch. 1 2 
1 IRQ0 interrupt request on the base timer ch. 1 
0 No IRQ1 interrupt request on the base timer ch. 0 1 
1 IRQ1 interrupt request on the base timer ch. 0 
0 No IRQ0 interrupt request on the base timer...

 
4. Registers 
 
4.18.  IRQ32/33 Batch Read Register (IRQxxMON) 
IRQ32MON indicates all of the interrupt requests allocated to interrupt vector no. 48. 
IRQ33MON indicates all of the interrupt requests allocated to interrupt vector no. 49. 
IRQ32MON shows the status of  the interrupt request on the CAN ch. 0. 
IRQ33MON shows the status of  the interrupt request on the CAN ch. 1. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved...

 
4. Registers 
 
4.19.  IRQ34 Batch Read Register (IRQ34MON) 
IRQ34MON indicates all of the interrupt requests allocated to interrupt vector no. 50. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved USB0INT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:5] Reserved: Reserved bits  Reads out 0. 
 
[bit4:0] USB0INT: 
bit no.  bit  Description 
0 No Endpoint 5 DRQ interrupt...

 
4. Registers 
 
4.20.  IRQ35 Batch Read Register (IRQ35MON) 
IRQ35MON indicates all of the interrupt requests allocated to interrupt vector no. 51. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved USB0INT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:6] Reserved: Reserved bits  Reads out 0. 
 
[bit5:0] USB0INT: 
bit no.  bit  Description 
0 No status (SOFIRQ, CMPIRO)...

 
4. Registers 
 
4.21.  IRQ36/37 Batch Read Register (IRQxxMON) 
IRQ36MON indicates all of the interrupt requests allocated to interrupt vector no. 52. 
IRQ37MON indicates all of the interrupt requests allocated to interrupt vector no. 53. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15  0 
Field Reserved 
Attribute R 
Initial  value  0x0000 
 
[bit31:0] Reserved: Reserved bits  Reads out 0. 
 
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4. Registers 
 
4.22.  IRQ38/39/40/41/42/43/44/45 Batch Read Register (IRQxxMON) 
IRQ38MON indicates all of the interrupt requests allocated to interrupt vector no. 54. 
IRQ39MON indicates all of the interrupt requests allocated to interrupt vector no. 55. 
IRQ40MON indicates all of the interrupt requests allocated to interrupt vector no. 56. 
IRQ41MON indicates all of the interrupt requests allocated to interrupt vector no. 57. 
IRQ42MON indicates all of the interrupt requests allocated to interrupt...

 
4. Registers 
 
4.23.  IRQ46/47 Batch Read Register (IRQxxMON) 
IRQ46MON indicates all of the interrupt requests allocated to interrupt vector no. 62. 
IRQ47MON indicates all of the interrupt requests allocated to interrupt vector no. 63. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15  0 
Field Reserved 
Attribute R 
Initial  value  0x0000 
 
[bit31:0] Reserved: Reserved bits  Reads out 0. 
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CHAPTER  6: Interrupts 
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5. Usage Warnings 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Interrupts 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  40  
5. Usage Warnings 
Be careful with the following points when using the interrupt controller. 
  The interrupt request signals from each of the peripheral resources ar e notified by level. When exiting 
from interrupt processing, always clear the interrupt request. 
 
   The NMIX pin is allocated shared with a general-purpo se port. The initial value after reset is released is 
configured...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
164 
MB9Axxx/MB9Bxxx  Series