Fujitsu Series 3 Manual

 
4. Registers 
 
bit no.  bit Description 
0 The EP2 DRQ interrupt of the USB ch. 0 is output as a request to the CPU. 1 
1 The EP2 DRQ interrupt of the USB ch. 0 is output as a transfer request to the DMAC. 
0 The EP1 DRQ interrupt of the USB ch. 0 is output as a request to the CPU. 0 
1 The EP1 DRQ interrupt of the USB ch. 0 is output as a transfer request to the DMAC. 
MFS: Multifunction serial interface 
 
 
  When  ch

anging the DRQSEL settings during a DMA tr ansfer, clear all of the interrup
 t...

 
4. Registers 
 
4.2.  EXC02 Batch Read Register (EXC02MON) 
EXC02MON indicates all of the interrupt requests allocated to interrupt vector no. 2. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 1098765432 1 0 
Field Reserved HWINT NMI 
Attribute  R R R R R R RRR RRR RR  R  R 
Initial 
value  0 0 00 0 0 00000000 0 0 
 
[bit31:2] Reserved: Reserved bits  Reads out 0. 
 
[bit1] HWINT: 
bit Description 
0  No hardware watchdog timer interrupt request 
1 Hardware...

 
4. Registers 
 
4.3.  IRQ00 Batch Read Register (IRQ00MON) 
IRQ00MON indicates all of the interrupt requests allocated to interrupt vector no. 16. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved FCSINT
Attribute  R R R R R R  R R R R R R  R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:1] Reserved: Reserved bits  Reads out 0. 
 
[bit0] FCSINT: 
bit Description 
0  No anomalous frequency detection by CSV...

 
4. Registers 
 
4.4.  IRQ01 Batch Read Register (IRQ01MON) 
IRQ01MON indicates all of the interrupt requests allocated to interrupt vector no. 17. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved SWWDTINT
Attribute  R R R R R RR RR RR RR R R  R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:1] Reserved: Reserved bits  Reads out 0. 
 
[bit0] SWWDTINT: 
bit Description 
0 No software watchdog  timer interrupt request...

 
4. Registers 
 
4.5.  IRQ02 Batch Read Register (IRQ02MON) 
IRQ02MON indicates all of the interrupt requests allocated to interrupt vector no. 18. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved LVDINT
Attribute  R R R R R R  R R R R R R  R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:1] Reserved: Reserved bits  Reads out 0. 
 
[bit0] LVDINT: 
bit Description 
0  No low voltage detection (LVD) interrupt...

 
4. Registers 
 
4.6.  IRQ03 Batch Read Register (IRQ03MON) 
IRQ03MON indicates all of the interrupt requests allocated to interrupt vector no. 19. 
bit 31   16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved WAVE1INT WAVE0INT 
Attribute  R R R R R R R R  R R R R R R R  R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:8] Reserved: Reserved bits  Reads out 0. 
 
[bit7:4] WAVE1INT: 
bit no.  bit  Description 
0 No WFG timer 54...

 
4. Registers 
 
4.7.  IRQ04/05 Batch Read Register (IRQxxMON) 
IRQ04MON indicates all of the interrupt requests allocated to interrupt vector no. 20. 
IRQ05MON indicates all of the interrupt requests allocated to interrupt vector no. 21. 
IRQ04MON shows the status of  the interrupt requests on the external interrupt from ch.0 to ch.7. 
IRQ05MON shows the status of  the interrupt requests  on the external interrupt from ch.8 to ch.15. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000...

 
4. Registers 
 
4.8.  IRQ06 Batch Read Register (IRQ06MON) 
IRQ06MON indicates all of the interrupt requests allocated to interrupt vector no. 22. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved QUD1INT QUD0INT TIMINT
Attribute  R R R R  R R R R  R R R R R R R  R 
Initial 
value  0 0 0 0 0 0 
0 0 0 0  0 0 0 0 0 0 
 
[bit31:14] Reserved: Reserved bits  Reads out 0. 
 
[bit13:8] QUD1INT: 
bit no.  bit  Description 
0 No PC...

 
4. Registers 
 
[bit7:2] QUD0INT: 
bit no. bit  Description 
0 No PC match & RC match interrupt request on QPRC ch. 0 7 
1 PC match & RC match interrupt request on QPRC ch. 0 
0 No interrupt request detected RC out of range on QPRC ch. 0 6 
1 Interrupt request detected RC out of range on QPRC ch. 0 
0 No PC counter direction change interrupt request on QPRC ch. 0 5 
1 PC counter direction change interrupt request on QPRC ch. 0 
0 No overflow/underflow/zero index interrupt request on QPRC ch. 0 4 
1...

 
4. Registers 
 
4.9. IRQ07/09/11/13/15/17/19/21 Batch Read Register 
(IRQxxMON) 
IRQ07MON indicates all of the interrupt requests allocated to interrupt vector no. 23. 
IRQ09MON indicates all of the interrupt requests allocated to interrupt vector no. 25. 
IRQ11MON indicates all of the interrupt requests allocated to interrupt vector no. 27. 
IRQ13MON indicates all of the interrupt requests allocated to interrupt vector no. 29. 
IRQ15MON indicates all of the interrupt requests allocated to interrupt...