Fujitsu Series 3 Manual

 
2. Configuration 
 
2. Configuration 
This section shows the block diagram of the Low-voltage Detection Circuit. 
 Block diagram of Low-vo ltage Detection Circuit 
 
 Low-voltage Detection Voltage Control Register 
This register controls whether to enable monitoring the power supply voltage for a low-voltage detection 
interrupt and specifies the detection volta ge for a low-voltage detection interrupt. 
 Low-voltage Detection Voltage Protection Register 
This register write-protects the Low-voltage...

 
2. Configuration 
 
 Pins of Low-voltage  Detection Circuit 
The following shows the pins used in the Low-voltage Detection Circuit. 
  VCC pin 
The Low-voltage Detection Circuit monitors the power supply voltage of this pin. 
   VSS pin 
This pin is a GND pin used as a basis to detect the power supply voltage. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  4: Low-voltage  Detection 
MN706-00002-1v0-E 
86 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.  Explanation of Operations 
This section explains the operations of the Low-Voltage Detection Reset Circuit and the 
Low-voltage Detection Interrupt Circuit. 
 Operations of Low-Voltage Detection Reset Circuit 
  Operations 
The Low-Voltage Detection Reset Circuit always enters a monitoring state after power-on. This circuit 
generates a reset signal when the power supply voltage (VCC) falls below the detection voltage. A reset is 
released when the power supply...

 
3. Explanation of Operations 
 
 Operations of Low-voltage Detection Interrupt Circuit 
  Operations 
The Low-voltage Detection Interrupt Circuit monitors  the power supply voltage (VCC) and generates an 
interrupt signal when the power supply voltage falls below the specified value. 
An interrupt request is enabled when 1 is set to the LVDIE bit of the Low-voltage Detection Voltage 
Control Register. The initial value is set to Not Enable (0). The interrupt detection voltage can be set by 
the SVHI...

 
3. Explanation of Operations 
 
 This circuit does not conduct monitoring the power supply vol
 tage if PCLK2 is gated by TIMER mode, 
STOP mode, or PBC2_PSR Register while waiting for the stabilization of the Low-voltage Detection 
Circuit. After checking that the status flag LVDIRDY is set to 1, change to the desired mode. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  4: Low-voltage  Detection 
MN706-00002-1v0-E 
89 
MB9Axxx/MB9Bxxx  Series  

 
4. Setup Procedure Examples 
 
4.  Setup Procedure Examples 
This section explains the procedures to set up the Low-voltage Detection Circuit, giving 
examples. 
Figure 4-1 Low-voltage detection interrupt setting 
FUJITSU SEMICONDUCTOR LIMITED 
 
Write 0x1ACCE553 to the LVD_RLR Register. 
Sta r t 
Clearing a low-voltage detection  interrupt cause. 
Release write protection mode of the LVD_CTL Register. 
Set the detection interrupt voltage to the LVD_CTL Register, and also set the  operation state to...

 
5. Registers 
 
5. Registers 
This section explains the configuration and functions of the registers used in the Low-voltage 
Detection Circuit. 
 List of Low-voltage Det ection Circuit Registers 
 
Abbreviation Register  name See 
LVD_CTL Low-voltage Detection Voltage Control Register  5.1 
LVD_STR Low-voltage Detection Interrupt Register  5.2 
LVD_CLR Low-voltage Detection Interrupt Clear Register  5.3 
LVD_RLR Low-voltage Detection Voltage Protection Register  5.4 
LVD_STR2 Low-voltage Detection...

 
5. Registers 
 
5.1.  Low-voltage Detection Voltage Control Register (LVD_CTL) 
The Low-voltage Detection Voltage Control Register (LVD_CTL) controls whether to enable 
monitoring the power supply voltage for a low-voltage detection interrupt and specifies the 
detection voltage for a low-voltage detection interrupt. 
 
Bit 7 6 5 4 3 2 1 0 
Field LVDIE Reserved SVHI Reserved 
Attribute  R/W - R/W  R/W R/W R/W  - - 
Initial value  0 1 0  0 0 0 0 0 
 
[bit 7] LVDIE: Low-voltage detection interrupt enable...

 
5. Registers 
 
[bit 1:0] Reserved: Reserved bits 0 is always set in read mode. 
This bit has no effect in write mode. 
 
 
  The l o

w-voltage detection interrupt enable bit (LVD IE) must be en
 abled after 0 was written to the 
LVDCL bit of the Low-voltage Detection Interrupt  Clear Register (LVD_CLR) to clear the interrupt 
request. 
   When the low-voltage detection interrupt enable bit (LVDIE) is not enabled, the Low-voltage Detection 
Circuit for detecting a low-voltage interrupt is stopped....

 
5. Registers 
 
5.2.  Low-voltage Detection Interrupt Register (LVD_STR) 
The Low-voltage Detection Interrupt Register (LVD_STR) holds a low-voltage detection 
interrupt cause. 
 Bit 7 6 5 4 3 2 1 0 
Field LVDIR Reserved 
Attribute  R - -  - - -  - - 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] LVDIR: Low-voltage detection interrupt bit 
Bit Description 
0  A low-voltage detection interrupt request is not detected. [Initial value] 
1 A low-voltage detection interrupt request has been detected. 
 
[bit...