Fujitsu Series 3 Manual

 
3. Explanation of Operations 
 
3.3. Reset Sequence 
This model initiates the hardware the program and hardware operations starting with the initial 
state when a reset cause is cleared.   
A series of operations starting with the reset and ending with the initiation of the operations is 
called a reset sequence.   
The following explains a reset sequence. 
 State Transition Diagram for Resets 
The following diagram shows a transition of reset states. The detailed operations are given in the...

 
3. Explanation of Operations 
 
1. Capturing reset causes 
Reset causes are captured and retained until a reset is issued to the device. 
2.  Issuing resets 
When a reset is ready to be issued, a device internal reset is issued. 
3.  Clearing resets 
When a reset cause is cleared, a device internal reset is extended for the amount of time required to clear 
the reset (for example, a wait required until oscilla tion of a high-speed CR has become stable). When 
the extended period of time has expired,...

 
3. Explanation of Operations 
 
3.4.  Operations After Resets are Cleared 
 PONR, LVDH, INITX, HWDG R, SWDGR, CSVR, FCSR 
Figure 3-1 provides an example of the operation waveform  after a cause of INITX pin input reset ha s been 
cleared. 
Figure 3-1 Operation Waveform After INITX Pin Input Reset has been Cleared 
INITX
Internal reset
Oscillation of 
low-speed CR
Wait time required until oscillation of high- speed CR has become stable
Oscillation of 
high-speed CR
Dozens cycle
Start operation
Clear...

 
4. Registers 
 
4. Registers 
This section explains the configuration and functions of the registers. 
 Register list 
 
Abbreviation Register  name See 
RST_STR Reset cause register  4.1 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
78 
MB9Axxx/MB9Bxxx  Series  

 
4. Registers 
 
4.1.  Reset Cause Register (RST_STR: ReSeT STatus Register) 
The reset cause register shows causes of resets that have just occurred and initializes values 
upon power up. 
Reading the register clears all bits.   
It stores all reset causes that have been generated until after it has been read upon power up. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved SRST 
Attribute  - - -  - - - - R 
Initial value  - - -  - - - - 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field FCSR  CSVR HWDT SWDT...

 
4. Registers 
 
[bit 5] HWDG: Hardware watchdog reset flag Indicates a reset from the hardware watchdog timer. 
If the timer underflows, a reset is issu ed and HWDT is enabled (HWDT = 1). 
bit Description 
0 A hardware watchdog reset has not been issued. 
1 A hardware watchdog reset has been issued. 
 
[bit 4] SWDG: Software watchdog reset flag  Indicates a reset from the software watchdog timer. 
If the timer overflows, a reset is issu ed and SWDT is enabled (SWDT = 1). 
bit Description 
0 A software...

 
4. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Resets 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  18 
 
This register is initialized by a power-on reset or low- voltage detection reset. It is not initialized by any 
other reset causes. Reading th e register clears all bits. 
 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
81 
MB9Axxx/MB9Bxxx  Series  

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
82 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
Chapter: Low-voltage Detection 
This chapter explains the functions and operations of the Low-voltage Detection Circuit. 
 
1.
 Overview 
2. Configuration 
3. Explanation of Operations 
4. Setup Procedure Examples 
5. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFLVD-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  4: Low-voltage  Detection 
MN706-00002-1v0-E 
83 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
The Low-voltage Detection Circuit monitors the power supply voltage, and generates reset 
and interrupt signals when the power supply voltage falls below the detection voltage. 
 Overview of Low-volt age Detection Circuit 
  Operations of Low-voltage Reset Circuit 
  This circuit monitors the power supply voltage (VCC) and generates a reset signal when the power 
supply voltage falls below the specified value. 
   This circuit always monitors the power supply voltage. 
...