Fujitsu Series 3 Manual

 
1. Overview 
 
Chapter: Resets 
This chapter explains the function and operation of the resets. 
 1.
 Overview 
2. Configuration 
3. Explanation of Operations 
4. Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFRESET-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
65 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
This product has the following reset causes and issues a reset to initialize a device upon 
accepting a reset cause. 
  Power-on reset 
   INITX pin input 
   External power supply/low-voltage detection reset 
   Software watchdog reset 
   Hardware watchdog reset 
   Clock failure detection reset 
   Anomalous frequency detection reset 
   Software reset 
   TRSTX pin input 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
66 
MB9Axxx/MB9Bxxx...

 
2. Configuration 
 
2. Configuration 
 Block Diagram of Resets 
SW-WDG
HW-WDG
CSV
INITX
LVDH
PONR
TRSTX
PORESETn
SYSRESETn
nTRST
SQ-WDG reset
HW-WDG reset
Clock failure detection reset
Anomalous frequency detection reset
HRESET SYSRESETREQ
SYSRESETREQ
SYSRESETn
PRESET0
PRESET1
PRESET2
Reg
Reg
 
 
PONR : Power-on reset 
INITX  :  INITX pin input reset 
LVDH  :  Low-voltage detection reset 
TRSTX  :  TRSTX pin input reset 
HRESET  :  AHB bus reset (a bus reset issued by all reset causes) 
PRESET0, 1, 2...

 
3. Explanation of Operations 
 
3.  Explanation of Operations 
This section explains the operations of the resets. 
3.1 Reset Causes   
3.2  Resetting Inside the Device 
3.3  Reset Sequence 
3.4  Operations After Resets are Cleared 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
68 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.1. Reset Causes 
This section explains reset causes. 
 Power-On Reset (PONR) 
A reset that is generated at power-up. 
Generated by  This signal is generated by de tecting a rising edge of the power supply. 
Cleared by This signal is automatically cleared after issuing a reset. 
Initialization 
target  Initializes all register settings and hardware. 
Flag 
Bit 0 (PONR) of reset cause register (RST_STR) = 1 
 INITX Pin Input Reset (INITX) 
A reset that is externally...

 
3. Explanation of Operations 
 
 Hardware Watchdog Reset (HWDGR) 
A reset that is input from the hardware watchdog timer. 
Generated by  This signal is generated when the hardware watchdog timer underflows. 
Cleared by  This signal is automatically cleared after issuing a reset. 
Initialization 
target  Initializes all register settings and hardware except the debug circuit. 
Note:  The reset cause register is not initialized. 
Flag 
Bit 5 (HWDT) of reset cause register (RST_STR) = 1 
 Clock Failure...

 
3. Explanation of Operations 
 
 Software Reset (SRST) 
A reset that is generated when an access to  the reset control register occurs. 
Generated by  This signal is generated by a write to 
the reset control register (SYSRESETREQ 
bit). 
Cleared by  This signal is automatically cleared after issuing a reset. 
Initialization 
target  Initializes all register settings and hardware except the following: 
Registers that are not initialized by a software reset 
  Debug circuit 
   All registers related...

 
3. Explanation of Operations 
 
3.2.  Resetting Inside the Device 
This section explains the internal reset signals of this device. 
Resets that are internally connected to the device are divided into resets that are input to the Cortex-M3 core 
and resets that are input to peripheral circuits. 
 
3.2.1  Resets to Cortex-M3 
3.2.2  Resets to Peripheral Circuit 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  3: Resets 
MN706-00002-1v0-E 
72 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.2.1. Resets to Cortex-M3 
The device has three reset inputs to the Cortex-M3: PORESETn, SYSRESETn, and nTRST. 
The following provides reset causes for these three reset inputs. 
 Power-on reset PORESETn 
Reset Causes  
  Power-on reset (PONR) 
   Low-voltage detection reset (LVDH) 
 System reset SYSRESETn 
Reset Causes  
  Power-on reset (PONR) 
   Low-voltage detection reset (LVDH) 
   INITX pin input (INITX) 
   Software watchdog reset (SWDGR) 
   Hardware...

 
3. Explanation of Operations 
 
3.2.2. Resets to Peripheral Circuit 
The bus resets (HRESET, PRESET0, PRESET1, and PRESET2) that are input to the 
peripheral circuit are basically generated by all reset causes. Resetting of PRESET1 and 
PRESET2 can be controlled by register settings. 
The following provides reset causes for the bus resets. 
 Resets to Peripheral Circuit 
  HRESET and PRESET0 
Reset Causes  
  Power-on reset (PONR) 
   Low-voltage detection reset (LVDH) 
   INITX pin input (INITX)...