Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
5.7.  Software Watchdog Clock Prescaler Register (SWC_PSR) 
The SWC_PSR sets the frequency division and enables the output of the software watchdog 
clock. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field TESTB Reserved SWDS 
Initial value 1’bx  -  2b00 
Attribute R/W  - R/W 
 Register functions 
[bit 7] TESTB: TEST bit 
Bit Description 
0 No permitting. 
1  Always written by “1”   
 
[bit 7:2] RES: Reserved bits 
0b100000 is read from these bits. 
Set these bits to...

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5.8.  Trace Clock Prescaler Register (TTC_PSR) 
The TTC_PSR sets the trace clock frequency division. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  TTC 
Initial value - 1b0 
Attribute -  R/W 
 Register functions 
[bit 7:1] RES: Reserved bits 
0b0000000 is read from these bits. 
Set these bits to 0b0000000 when writing. 
[bit 0] TTC: Trace clock frequency division ratio setting bit 
Bit Description 
0 1/1 [Initial value] 
1 1/2 
 
  This reg i

ster is...

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5.9.  Clock Stabilization Wait Time Register (CSW_TMR) 
CSW_TMR sets the oscillation stabilization wait time of the main/sub clock. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved SOWT  MOWT 
Initial value -  3b000  4b0000 
Attribute - R/W  R/W 
 Register functions 
[bit 7] RES:    Reserved bits 
0b0 is read from this bit. 
Set this bit to 0b0 when writing. 
[bit 6:4] SOWT: Sub clock stabilization wait time setup bit 
Bit 6  Bit 5Bit 4  Description 
0 0 0...

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   Set each oscillation stabilization wait time before enab ling the oscillation enable bit of the 
 SCM_CTL. 
If you change MOWT or SOWT while waiting for osc illation stability of each oscillator, each oscillation 
stabilization wait time is not guaranteed. 
   This register is not initialized by software reset. 
 
 
CHAPTER  2-1: Clock 
MN706-00002-1v0-E 
38 
MB9Axxx/MB9Bxxx  Series  

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5.10.  PLL Clock Stabilization Wait Time Setup Register (PSW_TMR) 
The PSW_TMR sets the PLL clock stabilization wait time. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  PINC Reserved POWT 
Initial value  - 1b0 -  3b000 
Attribute -  R/W -  R/W 
 Register functions 
[bit 7:5] RES: Reserved bits 
0b000 is read from these bits. 
Set these bits to 0b000 when writing. 
[bit 4] PINC: PLL input clock select bit 
Bit Description 
0  Selects CLKMO (main...

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5.11.  PLL Control Register 1 (PLL_CTL1) 
The PLL_CTL1 sets the PLL frequency division ratio. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field PLLK  PLLM 
Initial value 4b0000  4b0000 
Attribute R/W  R/W 
 Register functions 
[bit 7:4] PLLK: PLL input clock frequency division ratio setting bit 
Bit 7:4  Description 
0000 
0001 
 
 
1111  The frequency division is 1/(PLLK+1). 
Example: PLLK=0000 +1 => 1/1 frequency [Initial value] 
 
[bit 3:0] PLLM: PLL VCO clock...

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5.12.  PLL Control Register 2 (PLL_CTL2) 
The PLL_CTL2 sets the PLL frequency division ratio. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  PLLN 
Initial value   5b00000 
Attribute -  R/W 
 Register functions 
[bit 7:5] RES: Reserved bits 
0b000 is read from these bits. 
Set these bits to 0b000 when writing. 
[bit 4:0] PLLN: PLL feedback frequency division ratio setting bit 
Bit 4:0  Description 
00000 
00001 
・ 
・ 
11111  The frequency division is...

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5.13.  Debug Break Watchdog Timer Control Register (DBWDT_CTL) 
The DBWDT_CTL sets the watchdog timer count operation for debug mode tool break. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field DPHWBE  Reserved DPSWBE Reserved 
Initial value 1b0 1b0 1b0   
Attribute R/W - R/W   
 Register functions 
[bit 7] DPHWBE: HW-WDG debug mode break bit 
Bit Description 
0  HW-WDG stops counting at the tool break [Initial value] 
1 HW-WDG continues counting at the tool break...

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5.14.  Interrupt Enable Register (INT_ENR) 
The INT_ENR enables/disables interrupts. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field  Reserved FCSE  Reserved PCSE SCSE MCSE 
Initial value     1b0    1b0 1b0 1b0 
Attribute     R/W    R/W R/W R/W 
 Register functions 
[bit 7:6] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 5] FCSE: Anomalous frequency detection interrupt enable bit   
Bit Description 
0 Disables FCS...

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5.15.  Interrupt Status Register (INT_STR) 
The INT_STR indicates the status of interrupts. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field  Reserved FCSI  Reserved PCSI SCSI MCSI 
Initial value     1b0    1b0 1b0 1b0 
Attribute     R    R R R 
 Register functions 
[bit 7:6] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 5] FCSI: Anomalous frequency detection interrupt status bit 
Bit Description 
0  No FCS interrupt...