Fujitsu Series 3 Manual

 
2. Memory Architecture 
 
2. Memory Architecture 
This chapter shows this series memory architecture.   
For this series, 4G-byte address space is available. 
Maximum 1M-byte FLASH area, maximum 512K-byte on-chip SRAM area, and maximum 512K-byte 
code SRAM area are defined. 
Also, as an external bus area, 2G-byte area from 0x60000000 to 0xDFFFFFFF is defined. An external 
memory device can be connected to this area. 
Clause 2.1 illustrates the memory map, and Clause 2.2 illustrates the peripheral...

 
2. Memory Architecture 
 
2.1. Memory Map 
Figure 2-1 illustrates this series memory map.   
Figure 2-1 Memory Map 
0x4000 _0000
0x4000 _1000 0x4001 _0000 0x4001 _1000 0x
4001 _2000
0x

4001 _3000
0x4001 _5000
0x4001 _6000 0x4002 _0000
0x4002 _1000
0x4002 _2000 0x4002 _4000 0x4002 _5000
0x4002 _6000 0x4002 _7000 0x4002 _8000 0x4002 _E000
0x4002 _F000 0x4003 _1000
0x4003 _0000 0x4003 _2000
0x4003 _3000 0x4003 _4000
0x4003 _5000 0x4003 _6000
0x4003 _7000
0x4003 _8000
0x4003 _9000
0x4003 _A000
0x4003...

 
2. Memory Architecture 
 
2.2. Peripheral Address Map 
Table 2-1 shows this series peripheral address map. 
Table 2-1 Peripheral Address Map 
Start Address End Address Bus  DMAC
TransferPeripheral Register 
Map  Details 
0x4000_0000 0x4000_0FFF 
FLASH IF Register FLASH_IF *1 
0x4000_1000 0x4000_FFFF  AHB 
Disabled
Reserved - 
- 
0x4001_0000 0x4001_0FFF  Clock and Reset Control  Clock / 
Reset  Chapter 2
Chapter 3
Chapter 5
Chapter 10
0x4001_1000 0x4001_1FFF  Hardware Watchdog Timer HWWDT Chapter 11...

 
2. Memory Architecture 
 
 
Start Address End Address  Bus DMACTransferPeripheral  Register 
Map  Details 
0x4003_0000 
0x4003_0FFF  External Interrupt EXTI Chapter 7 
0x4003_1000 0x4003_1FFF  Interrupt Source Check 
Register INT-Req 
READ  Chapter 6 
0x4003_2000 0x4003_2FFF 
Reserved - - 
0x4003_3000 0x4003_3FFF  GPIO GPIO Chapter 9 
0x4003_4000 0x4003_4FFF  Reserved - - 
0x4003_5000 0x4003_5FFF  Low Voltage Detection LVD Chapter 4 
0x4003_6000 0x4003_6FFF  USB Clock Generation 
Circuit USB 
Clock...

 
3. Cortex-M3 Architecture 
 
3. Cortex-M3 Architecture 
This chapter explains the core architecture used in this series.   
Cortex-M3 core block architecture used in this series is as follows: 
  Cortex-M3 Core 
   NVIC 
   MPU 
 
   DWT 
   ITM 
   FPB 
   ETM 
   SWJ-DP 
   TPIU 
   ROM Table 
 Cortex-M3 Core 
High-performance 32-bit processor core (ARM Cortex-M3 core) is equipped with this series. 
This peripheral manual does not describe the details of Cortex-M3 core. 
For the details,...

 
3. Cortex-M3 Architecture 
 
  SysTick Timer 
SysTick Timer is a system timer for OS task management integrated into NVIC. 
This series generates STCLK through dividing HCLK by eight and sets the values of SysTick 
Calibration Value Register (0xE000E01C) as shown below: 
  [Bit 31]  :  NOREF = 0 
  [Bit 30]  :  SKEW = 1 
  [Bit 23:0]  :  TENMS = 0x0186A0 (100000)*1 
 
*1 :  TENMS value is set to a value which becomes 10ms when 1/8 clock of HCLK is input to STCLK and  that HCLK is in 80MHz (10MHz in...

 
4. Mode 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: System Overview 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  12 
4. Mode 
This chapter explains operating modes.   
In this product line, the following operating modes can be used: 
   User Mode 
Internal ROM(Flash) Startup : CPU obtains a re set vector from Flash and starts operations. 
   Serial Writer Mode 
Flash serial write is enabled. 
* : For the details of this mode, see Flash Programming Manual. 
Operating modes are determined after a release of resp...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
12 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Clock 
This chapter explains the operating clock. 
 
1.
 Clock Generation Unit Overview 
2. Clock Generation Unit Configuration/Block Diagram 
3. Clock Generation Unit Operations 
4. Clock Setup Procedure Examples 
5. Clock Generation Unit Register List 
6. Clock Generation Unit Usage Precautions 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFCLOCK-E02.1 
CHAPTER  2-1: Clock 
MN706-00002-1v0-E 
13 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
1.  Clock Generation Unit Overview 
This section provides an overview of the clock generation unit. 
The clock generation unit generates various types of clocks used to operate the MCU. 
Source clock is the generic name for external and internal oscillation clocks of this MCU. 
The following five types of clocks are source clocks: 
   Main clock (CLKMO) 
   Sub clock (CLKSO) 
   High-speed CR clock (CLKHC) 
   Low-speed CR clock (CLKLC) 
   PLL clock (CLKPLL) 
 
Select...