Fujitsu Series 3 Manual

 
 
 
 
Page Section Change Results 
377 CHAPTER 13-2 
Watch Counter  2. Configuration of the Watch Counter 

  Corrected the error in description. (Watch counter control register 
(WCRD)   (WCCR)) 
407 3.2.  I/O mode 
   Corrected  of   I/O mode 8 (Shared channel signal 
trigger and timer start/stop mode. 
(  The odd channel stops...    Base timer stops...) 
409 to 412  CHAPTER 14-1 
Base Timer I/O Select 
Function 
4.1., 4.2. I/O Select Register (BTSEL0123, BTSEL4567) 
   Corrected the bit...

 
 
 
 
Page Section Change Results 
658 3. Operations 
     RC_Mode1 (QCR:RCM[1:0]=01): 
Added . 
659      RC_Mode3 (QCR:RCM[1:0]=11): 
Added . 
661      Operation example of QPRC Maximum Position Register 
(QMPR) interrupt 
The following ... RC_Mode2 (QCR:RCM[1:0]).    
The following ... RC_Mode2 (QCR:RCM[1:0]=10). 
662      Position counter reset mask function 
  Deleted the description of the ZIN function is set to the counter 
clear function (QCR:CGSC=0) and when. 
664      Position...

 
 
 
 
Page Section Change Results 
696 3.1.1. Scan conversion operation 
   Corrected the title of Figure 3-1, Figure 3-2. (SCIS0=0x04   
0x08) 
706  3.2.4. Interrupts in priority conversion 
   Corrected . (PFS[3:0]   PFS[1:0]) 
710  3.4. Starting DMA 
   Corrected the whole description and the figure. 
713  4.2. Priority conversion setup procedure example 
   Corrected Figure 4-2. (SFCLR   PFCLR) 
714  CHAPTER 18-2 
10-bit A/D  Converter 
4.3. Setting the conversion time 
  Corrected the...

 
 
 
 
Page Section Change Results 
912 1. Overview of LIN Interface (Ver. 2.1) (LIN Communication 
Control Interface Ver. 2.1) 
   128 bytes   128 × 9 bits 
923, 924  3.1. Baud rate settings 
   Corrected Figure  3-1. (11xFL  10xFL) 
   Corrected the computation expression in   Allowable baud rate 
range for data reception. 
   Corrected the value in the table. 
941, 942  6.1. Serial Control Register (SCR) 
   Added  of [bit15]. 
   Corrected the descri ption of [bit12].   
(SSR:LER, FRE, ORE...

 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MAJOR CHANGES IN THIS EDITION 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  11 
 
Page Section  Change Results 
1319 FLASH_IF 
  Corrected the initial value of FSTR(0x008). 
(-------- -------- -------- -----00X   -------- -------- -------- ------0X) 
   Added CRTRMM(0x100). 
1320 Clock/Reset 
  Corrected the initial value of RST_STR(0x00C). 
(-------0 00000-01   -------0 0000--01) 
1321 SW  WDT 
   Corrected the initial value of WdogLock(0xC00). 
(00000000 00000000...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05034\051 
MB9Axxx/MB9Bxxx  Series  

 
1. Bus Architecture 
 
CHAPTER: System Overview 
This chapter explains this series system overview.   
 1.
 Bus Architecture 
2. Memory Architecture 
3. Cortex-M3 Architecture 
4. Mode 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFSYSTEM-E01.3 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  1: System  Overview 
MN706-00002-1v0-E 
1 
MB9Axxx/MB9Bxxx  Series  

 
1. Bus Architecture 
 
1. Bus Architecture 
This chapter explains this series bus architecture. 
For this series bus, AHB Bus Matrix circuit actualizes a multi-layer bus. Master and slave architectures are 
shown below:   
  Master 
  Cortex-M3 CPU(I-code Bus, D- code Bus, System Bus) 
   DMAC 
 
  Slave 
  Internal Flash Memory 
   Internal SRAM(Code SRAM, On-chip SRAM) 
   External Bus 
   USB ch0/1 
   AHB-AHB Bus Bridge 
   AHB-APB Bus Bridge (APB0, 1, 2) 
 
See  Figure 1-1  for the bus...

 
1. Bus Architecture 
 
   Bit-band operation must not be performed to a register which RMW is prohibited. 
   When Rea

d-Modify-Write process is performed over the software without bit-band operation, RMW 
signal is not output. 
Therefore, in this case, the flag value can be read  in read operation although a register supports RMW 
process, and it is necessary not to be cleared an unrelated flag mistakenly in write operation. 
   For the details of bit-band operations, see the Cortex-M3 Technical...

 
1. Bus Architecture 
 
1.1.  Bus Block Diagram 
Figure 1-1 illustrates this series bus block diagram.   
Figure 1-1 Bus Block Diagram 
Cortex-M3TM
Core FLASHIF FLASH 
ROM table 
ETM 
TPIU 
SWJ-DP Code SRAM
DMAC 
On chip SRAM
I-code bus
System bus
AHB to AHB
bridge 
USB ch0
CAN 
DMAC bus
AHB to APBbridge APB1 
Peripherals
EXT-Bus I/F 
 
AHB to 
APB bridge APB0 
Peripherals 
AHB to APB bridge 
D-code bus
AHB bus matrix 
APB0 
APB2 
APB1 
USB ch1
APB2 
Peripherals
 
 
There are  som

e areas which no DMAC...