Fujitsu Series 3 Manual

 
3. Operations of Standby Modes 
 
3.2.  Operations of TIMER modes (high speed CR timer, main timer, PLL timer, low speed CR timer, and sub 
timer modes) 
TIMER mode is used to stop supplying a base clock. This causes the CPU clock, AHB bus 
clock, and all APB bus clocks to  be stopped, leading to the further reduction of power 
consumption. In this case, all functions are stopped, excluding the oscillators, PLL, hardware 
watchdog timer, watch counter, clock failure detector, and Low Voltage Detection...

 
3. Operations of Standby Modes 
 
 Return from TIMER mode 
The CPU returns from TIMER mode in one of the following cases. 
  Return by reset 
If a reset (INITX pin input reset, low-voltage detection reset, hardware watchdog reset, or clock failure 
detection reset) occurs, the CPU changes to high speed CR run mode regardless of clock mode. 
Software watchdog reset and anomalous frequency detectio n reset are not available in this mode; therefore, 
the CPU cannot return by those resets. 
  Return by...

 
3. Operations of Standby Modes 
 
3.3.  Operations of STOP mode 
STOP mode is used to stop all oscillating operations. Enabling this mode stops all functions, 
excluding the Low Voltage Detection Circuit. This therefore allows data to be held with the 
minimum power consumption. 
 Functions of STOP mode 
  CPU and internal memory 
Enabling STOP mode stops CPU clocks and AHB bus clocks supplied to the internal memory or DMA 
controller. The contents of the internal memory are held. The debug function...

 
3. Operations of Standby Modes 
 
 Return from STOP mode 
The CPU returns from STOP mode  in one of the following cases. 
 Return by reset 
If a reset (INITX pin input reset or low-voltage detec tion reset) occurs, the CPU changes to the high speed 
CR run mode regardless of clock mode. 
Software watchdog reset, hardware watch dog reset,  clock failure detection reset, and anomalous frequency 
detection reset are not available in this mode; th erefore, the CPU cannot return by those resets. 
 Return...

 
3. Operations of Standby Modes 
 
 
   When  

an interrupt priority used for return is not set  at a level to return t
 he CPU, clock will be returned 
with the interrupt but the CPU remains stop state without returning. In order to do this, be sure to set the 
interrupt priority at a level which CPU is able to return. 
   If the transition to STOP mode is made during debugging, as the clock to the CPU stops, a return to RUN 
mode cannot be performed by the ICE. Use a return by reset or interrupt....

 
4. Standby Mode Setting Procedure Examples 
 
4.  Standby Mode Setting Procedure Examples 
This section provides standby mode setting procedure examples. 
Figure 4-1 Main timer mode setting procedure example 
Write KEY=0x1ACC and 
STM=0b00 to the STB_CTL  Register together.
SLEEPDEEP=1 setting
End
Start
Execute the WFI or WFE  instruction.
NoUSB used?
Yes
Write SUSPIE=0 to the UDCIE Register.Write USTP=1 to the UDCC Register.
Write UCEN=0 to the UCCR Register. writing
Change to main timer mode....

 
4. Standby Mode Setting Procedure Examples 
 
Figure 4-2 Stop mode setting procedure example (Main clock is selected as a master clock.) 
Write KEY=0x1ACC and 
STM=0b10 to the STB_CTL  Register together.
SLEEPDEEP=1 setting
End
Start
Execute the WFI or WFE 
instruction.
NoUSB used?
Yes
Write SUSPIE=0 to the UDCIE Register.Write USTP=1 to the UDCC Register.
Write UCEN=0 to the UCCR Register.
writing
Change to STOP mode.
NoUCEN=0?
Yes
NoCAN used? Yes
Write Init=1 to the CTRLR Register.
 
 In case of...

 
5. List of Low Power Consumption Registers 
 
5.  List of Low Power Consumption Registers 
This section explains the configuration and functions of the registers used in standby mode. 
 List of Low Power Consumption Registers 
 
Abbreviation Register  name See 
STB_CTL Standby Mode Control Register  5.1 
 
 
For th

e Clock Mode Selection Regi ster, refer to Chap
 ter Clocks. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  5: Low  Power  Consumption  Mode 
MN706-00002-1v0-E 
122 
MB9Axxx/MB9Bxxx  Series  

 
5. List of Low Power Consumption Registers 
 
5.1.  Standby Mode Control Register (STB_CTL) 
The Standby Mode Control Register controls TIMER or STOP mode. The value written to the 
SPL or STM bit is effective only when 0x1ACC is simultaneously written to the KEY bit. 
 
Bit 31 30 29 28 27 2625242322212019 18 1716
Field KEY 
Attribute R/W 
Initial  value  0x0000 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved SPLReserved STM 
Attribute -  R/W- R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0...

 
5. List of Low Power Consumption Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Low Power Consumption Mode 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  27 
[bit1:0] STM: Standby mode selection bit  This bit selects whether to change to TIMER or STOP mode. 
Bit1 Bit0 Description 
0 0 TIMER mode [Initial value] 
0 1  Setting disabled 
1 0 STOP mode 
1 1 Setting disabled 
 
 
The value written to the SPL or STM bit in the Stan dby Mode Control Register (STB_CTL) is effective 
only when 0x1ACC is...