Fujitsu Series 3 Manual

 
2. Configuration of CPU Operation Modes 
 
2.  Configuration of CPU Operation Modes 
This section explains the configuration of CPU operation modes. 
 CPU operation mode transition diagram 
Figure 2-1  shows the CPU operation mode transition diagram. 
Figure 2-1 CPU operation mode transition diagram 
 
Power-on
Initialization power-on reset
High speed CR oscillation 
stabilization waiting
Low speed CR oscillation  stabilization waiting
High speed CR mode
Main mode
PLL mode
Low speed CR mode
Sub mode...

 
2. Configuration of CPU Operation Modes 
 
 High speed CR mode transition diagram 
In high speed CR mode, the high speed CR oscillator clock is used as a master clock. 
Figure 2-2 High speed CR mode transition diagram 
 
High speed CR run mode
High speed CR sleep mode
STOP mode
Program reset
High speed CR timer mode
High speed CR oscillation 
stabilization waiting
Other modeA-1   Transition to RUN mode 
        (Oscillation stabilization)
A-2   Start high speed CR oscillation .
A-1A-2
A-4   Software...

 
2. Configuration of CPU Operation Modes 
 
 Main mode transition diagram 
In main mode, the main oscillator clock is used as a master clock. 
Figure 2-3 Main mode transition diagram 
 
Main run mode
Main sleep mode
STOP mode
Program reset
Main timer mode
Main oscillation stabilization 
waiting
Other mode
B-1B-2
B-4B-5
B-3
B-6
B-7
B-8
B-7
B-9
B-7
B-10
B-1   Transition to RUN mode (MORDY=1)
B-2   Start main oscillation. (MORDY=0)
B-4   Software reset
B-5   Release software reset. B-3   Complete...

 
2. Configuration of CPU Operation Modes 
 
 Sub mode transition diagram 
In sub mode, the sub oscillator clock is used as a master clock. 
Figure 2-5 Sub mode transition diagram 
 
Sub run mode
Sub sleep mode
STOP mode
Program reset
Sub timer mode
Sub oscillation stabilization waiting
Other mode
D-1D-2
D-4D-5
D-3
D-6
D-7
D-8
D-7
D-9
D-7
D-10
D-1   Transition to RUN mode (SORDY=1)
D-2   Start sub oscillation. (SORDY=0)
D-4   Software reset
D-5   Release software reset . D-3   Complete oscillation...

 
2. Configuration of CPU Operation Modes 
 
 PLL mode transition diagram 
In PLL mode, the PLL clock is used as a master clock. 
Figure 2-6 PLL mode transition diagram 
 
PLL run mode
PLL sleep mode
STOP mode
Program reset
PLL timer mode
PLL oscillation stabilization waiting
Main mode
E-1E-2
E-4E-5
E-3
E-6
E-7
E-8
E-7
E-9
E-10
Main oscillation stabilization 
waiting
E-7
E-11
E-1   Transition to RUN mode (PLLRDY=1)
E-2   Start PLL oscillation. (PLLRDY=0)
E-4   Software reset
E-5   Release software...

 
3. Operations of Standby Modes 
 
3.  Operations of Standby Modes 
This section explains operations of standby modes. 
Standby modes are classified into three types: SLEEP modes (high speed CR sleep, main 
sleep, PLL sleep, low speed CR sleep, and sub sleep), TIMER modes (high speed CR timer, 
main timer, PLL timer, low speed CR timer, and sub timer), and STOP mode. 
 Clock operation states in standby modes 
The table below shows the states of the oscillator clock, CPU clock, AHB bus clock, and APB...

 
3. Operations of Standby Modes 
 
Table 3-2 Clock operation states in TIMER modes TIMER modes 
 High speed CR timer mode  Main  
timer mode  PLL  
timer mode  Low speed CR 
timer mode  Sub  
timer mode 
High speed 
CR clock  Operating Operating Operating 
Stopped Stopped 
Main clock Varies depending 
on the setting of 
the MOSCE bit.  Operating Operating Stopped Stopped 
PLL clock 
Setting disabled  Varies depending 
on the setting of 
the PLLE bit.  Operating Stopped 
Stopped 
Low speed 
CR clock...

 
3. Operations of Standby Modes 
 
 Return factors from standby modes 
The table below shows the factors by which the system  returns from the SLEEP, TIMER, and STOP modes. 
Table 3-4 Return factors from standby modes 
  SLEEP mode  TIMER mode STOP mode 
Return 
factors by 
reset 
  INITX pin input reset 
   Low-voltage detection reset 
   Software watchdog reset 
   Hardware watchdog reset 
   Clock failure detection reset 
   Anomalous frequency 
detection reset  
  INITX pin input reset 
...

 
3. Operations of Standby Modes 
 
3.1.  Operations of SLEEP modes (high speed CR sleep, main sleep, PLL sleep, low speed CR sleep, and sub 
sleep modes) 
SLEEP mode is classified as one of standby modes. Enabling SLEEP mode stops CPU 
clocks, reducing the power consumption. 
 Functions of SLEEP mode 
  CPU and internal memory 
In SLEEP mode, the CPU clock is stopped. However, the AHB bus clock continues to be active. The 
internal memory active and data is held. 
  Peripherals 
The APB0 bus clock is...

 
3. Operations of Standby Modes 
 
 SLEEP mode setting procedure 
Execute the following steps  to change to SLEEP mode. 
1.  Set 0 to the SLEEPDEEP bit of the  Cortex-M3 System Control Register. 
2.  Execute the WFI or WFE instruction. 
The system changes to the appropriate SLEEP mode  according to the current clock mode indicated in 
the RCM bit of the System Clock Mode Control Register (SCM_CTL). 
 
For the System Clock Mode Control Register (SCM_CTL), refer to Chapter Clocks. 
  Return from SLEEP...