Fujitsu Series 3 Manual

 
1. Overview 
 
CHAPTER: Interrupts 
This chapter explains the interrupt controller and peripheral interrupt requests. 
 
1.
 Overview 
2. Structure 
3. Exception and Interrupt Vectors 
4. Registers 
5. Usage Warnings 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFIRQC-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  6: Interrupts 
MN706-00002-1v0-E 
125 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
The interrupt controller determines the priority of interrupt requests and sends the requests to 
the CPU. The Cortex-M3 CPU core is equipped with the nested vectored interrupt controller 
(NVIC) internally within the core. Interrupt signals from several peripherals are aggregated 
and input to a single interrupt vector. The interrupt requests that have occurred can be 
checked using the interrupt request batch read register. Furthermore, for some of the interrupt 
sources,...

 
2. Structure 
 
2. Structure 
This section shows the structure of the relationship between the interrupt controller and DMA 
transfer requests. 
 Interrupt Controller and DMA Transfer Request Block Diagram 
 
Figure 2-1 Interrupt controller and DMA transfer request block diagram 
 
R-bus
周辺
リソースR-bus 周辺
リソースPeripheral  resources
DMA transfer requests - 32 sources
DMAC
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
DMA transfer request 
clear signal
NVIC
Interrupt signal
(capable of DMA 
transfer)
- 32...

 
3. Exception and Interrupt Vectors 
 
3.  Exception and Interrupt Vectors 
This section shows a vector table of the exceptions and interrupts input to the NVIC. 
Table 3-1 Exception and interrupt vectors Ve c t o r   No.  IRQ 
No.  Exception and Interrupt Source  Ve c t o r
Offset
0 -  Initial SP Value  0x00 
1 - Reset  0x04 
2 - Non-Maskable Interrupt (NMI) / Hardware Watchdog Timer  0x08 
3 - Hard Fault  0x0C
4 - Memory Management  0x10 
5 - Bus Fault  0x14 
6 - Usage Fault  0x18 
7-10 - Reserved...

 
3. Exception and Interrupt Vectors 
 
Ve c t o r  No.  IRQ 
No.  Exception and Interrupt Source  Ve c t o r
Offset
34 18  Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.5  0x88 
35 
19 Reception Interrupt Request of Mu lti-Function Serial Interface ch.6  0x8C
36 20 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.6  0x90 
37 
21 Reception Interrupt Request of Multi- Function Serial Interface ch.7  0x94...

 
3. Exception and Interrupt Vectors 
 
*: USB Interrupt Source 
Ve c t o r  No.  IRQ 
No.  USB Interrupt Source Flags 
50 
34 USB Function (DRQ of End Point 1 to 5)  DRQ (End Point 1 to 5) 
USB Function 
(DRQI of End Point 0, DRQO and each status) DRQI, DRQO, SPK, SUSP, 
SOF, BRST, CONF, WKUP 
51 35 
USB HOST (each status)  DIRQ, URIRQ, RWKIRQ, 
CNNIRQ, SOFIRQ, CMPIRQ 
  The priorities of the exceptions for vectors no. 4 to 15  can be configured using the System Handler Priority 
Registers (address...

 
4. Registers 
 
4. Registers 
This section explains the DMA transfer request selection register and the interrupt request 
batch read register. 
 DMA transfer request selection register  and interrupt request batch read 
register list 
Abbreviation Register  Name See 
DRQSEL DMA Transfer Request Selection Register  4.1 
EXC02MON EXC02 Batch Read Register  4.2 
IRQ00MON IRQ00 Batch Read Register  4.3 
IRQ01MON IRQ01 Batch Read Register  4.4 
IRQ02MON IRQ02 Batch Read Register  4.5 
IRQ03MON IRQ03 Batch...

 
4. Registers 
 
Abbreviation Register Name  See 
IRQ27MON IRQ27 Batch Read Register  4.13 
IRQ28MON IRQ28 Batch Read Register  4.14 
IRQ29MON IRQ29 Batch Read Register  4.15 
IRQ30MON IRQ30 Batch Read Register  4.16 
IRQ31MON IRQ31 Batch Read Register  4.17 
IRQ32MON IRQ32 Batch Read Register  4.18 
IRQ33MON IRQ33 Batch Read Register  4.18 
IRQ34MON IRQ34 Batch Read Register  4.19 
IRQ35MON IRQ35 Batch Read Register  4.20 
IRQ36MON IRQ36 Batch Read Register  4.21 
IRQ37MON IRQ37 Batch Read Register...

 
4. Registers 
 
4.1.  DMA Request Selection Register (DRQSEL) 
The DMA Request Selection Register (DRQSEL) selects whether interrupt signals that can 
start DMA transfers are output as interrupt requests to the CPU or output as transfer requests 
to the DMAC. If selected as a transfer request to the DMAC, the bit in the interrupt request 
batch read register (IRQxxMON, xx=00 to 47) that corresponds to the interrupt signal is 0. 
 
bit 31  0 
Field DRQSEL[31:0] 
Attribute R/W 
Initial  value  0x00000000...

 
4. Registers 
 
bit no.  bit Description 
0 The transmission interrupt of the MFS ch. 3 is output as a request to the CPU. 
19 
1 The transmission interrupt of the MFS ch. 3 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  3 is output as a request to the CPU. 18 
1 The reception interrupt of the MFS ch. 3 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 2 is output as a request to the CPU. 
17 
1 The transmission...