Fujitsu Series 3 Manual

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   26 
4.3.  DMAC Operation and Control Procedure for Hardware 
(EM=0)  Tr a n sfer 
This section describes DMAC operation and control procedure for hard ware (EM=0) transfer.  
Figure 4-5 Transitional Diagram of Hard ware (EM=0)  Transfer State  
 
Hardware(EM=0) DMA operationTransition by CPU
Transition by DMAC/Periperal
      2
         5,6,7
    4
Disable
DE=0 or EB=0 or
DH!=0000 or PB=1 initial:...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   27 
 Description of Ea ch State 
Disable state 
See the software transfer procedure.  
Wait -1st -trigger  state  
In this state, the channel to be controlled is enabled to perform transfer. A channel in this state waits for 
the first transfer request from a Peripheral to be asserted. It  also changes its state upon instruction from 
CPU.  
Transfer state  
In this state, the channel to be...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   28 
It is supposed that DMAC ’s transfer processing may be too slow to catch up with the generation interval 
of transfer requests from Peripheral.  In the case of Demand transfer, the transfer request signal remains 
asserted; therefore, as many as  TC+1 of transfers can be performed (Example 4 in Figure  4-6). 
Figure  4-6 Operation of Hardware- Demand Transfer 
 
  
 
DMA status Transfer 
Demand...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   29 
Figure  4-7 shows a case of Block transfer. In the case of Block transfer, the number of transfer requests 
required to complete the tra nsfer is TC+1. Unless the number of transfer requests goes over or below the 
requirement, CPU does not have to intervene (Example 1 in  Figure 4-7). 
Figure  4-7 Operation of Hardware- Block Transfer  
 
DMA status Transfer 
Block transfer mode (hardware DMA...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   30 
If the number of transfer requests generated from the Peripheral is smaller than DMAC ’s setting for the 
number of transfers, DMAC waits for the remaining number of transfer requests in Transfer state 
(Example 3 in Figure  4-7). 
It is supposed that DMAC’s transfer processing may be too slow to catch up with the generation interval 
of transfer requests from Peripheral. In the case of Block...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   31 
In the case of Demand transfer mode, the transfer request signal remains asserted from  the Pause state. 
Therefore, the transfer is resumed when DMAC returns to Transfer state, and the transfer request signal 
is cleared as normal. See Figure  4-8. 
Figure 4-8 Operation of Demand Transfer in Pause State  
 
DMA status
Transfer request Pause Transfer 
Demand transfer mode behavior during pause...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   32 
13.  Operation in Disable state and Wait -1st -trigger  state 
See  Step 11 in the software transfer procedure.  
If the transfer request signal is not asserted to the channel in Disable state, the specificati ons of the 
transfer content can be changed freely (rewriting to registers  DMACSA, DMACDA, DMACA[29:0], 
and  DMACB ). 
If the transfer request signal is asserted or may be asserted to the...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   33 
Figure  4-11  Operation of Demand Transfer in D isable State 
 
DMA status
Transfer requestWait 1st trigger Transfer 
Demand transfer mode behavior during disable state
Transfer action
Disable
DMA status
Transfer request
 Transfer 
Transfer actionDisable
Case of  transfer request be asserted during disable state Case of no transfer request be asserted during disable state
Wait 1st trigger
  
 
In...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   34 
Additional Matter 1  
See  Additional Matter 1 in the software transfer procedure.  
In the case of hardware transfer, always write "0"  t o  ST. 
Additional Matter 2  
See  Additional Matter 2 in the software transfer procedure.  
Additional Matter 3  
See  Additional Matter 3 in the software transfer procedure.  
Additional Matter 4  
See  Additional Matter 4 in the software transfer...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   35 
4.4.  DMAC Operation and Control Procedure for Hardware 
(EM=1) Transfer 
This section describes DMAC operation and control procedure for hardware (EM= 1) transfer.  
Figure 4-13  Transitional Diagram of Hardware (EM= 1) Transfer State  
 
Hardware (EM=1) DMA operation
      2
          5 ,6,7 
    4
Disable
DE
=0  or EB =0 or
DH !=0000  or PB=1
initial : SS=000
after stop :SS=code
Transfer
DE =1...