Fujitsu Series 3 Manual

 
2. Configuration, Block Diagram, and Operation 
 
2.  Configuration, Block Diagram, and Operation 
This section explains the configuration, block diagram, and operation of the I/O port. 
 Configuration of the I/O Port 
By setting registers of the I/O port, select Inpu t/Output direction and select GPIO/peripheral. 
Figure 2-1  shows the details of the I/O port. 
Figure 2-1 Block Diagram of the I/O Port 
  
PFR 
EPFR 
FUJITSU SEMICONDUCTOR LIMITED 
 
Peripheral output signal 2
If there is no 
output...

 
2. Configuration, Block Diagram, and Operation 
 
Ta b l e  2 - 1 describes register function. 
   The PFR, DDR, PD
IR, PDOR, and PCR register have 1-bit control register for each I/O port and select a 
function for the I/O port. 
   The ADE register has 1-bit control  register for each I/O port which doub les as an analog input pin and 
selects a function for the I/O port. 
   The SPSR register selects a function  for the I/O port which doubles as a USB pin or an oscillation pin. 
   The EPFR...

 
2. Configuration, Block Diagram, and Operation 
 
Ta b l e  2 - 2 lists pin functions which availability depends on selected I/O port functions and register setting 
values. 
Table 2-2 I/O Port Functions and Register Setting Values 
I/O Port Function 
Available main function  Available sub function ADE/
SPSR PFR
DDR PCR  EPFR
Special pin 
  Analog input 
  USB 
  Oscillation  N/A 1 - - Disconnect  *0 
GPIO function input pin 
Peripheral function input pin  0 Valid 
GPIO function output pin  GPIO...

 
2. Configuration, Block Diagram, and Operation 
 
 Initially Selected Functi ons for the I/O Port 
Ta b l e  2 - 3 describes initially selected functions fo r each I/O port after reset is released. 
Table 2-3 Initially Selected Functions for Each I/O Port after Reset Is Released 
No Pin Initially selected function 
1  TRSTX, TCK, TDI, TMS, TDO  JTAG pin is selected. Pull-up is enabled. 
2 ANxx  Can be used as an analog input pin. Digital input is cut off 
and 0 is input. 
3 X0A, 
X1A Can be used as an...

 
2. Configuration, Block Diagram, and Operation 
 
  Even if the input of one I/O port is connected to two or more peripheral functions, all peripheral inputs 
can be used by setting EPFR. For example, in  Figure 2-3, by selecting input for both Relocation input 
pin A_2 a n

d Relocation input pin B_1, simultaneous usage is possible. In this way, it is possible to use 
external interrupt and a multi-function serial input pin shared by one I/O port simultaneously. 
 
Figure 2-3 Multiple Peripheral...

 
2. Configuration, Block Diagram, and Operation 
 
   About Fixed Priority of EPFR Outputs 
  Only one output pin function among two or more outputs is allocated to one I/O port. 
By setting the EPFR register, if more than one output is  set, fixed priority is applied and output pins are 
selected.  Figure 2-4  shows output pins and fixed priority. 
 
Figure 2-4 Output Pins and Fixed Priority 
 
Fixed priority
functionPeripheral A output pin _0/
peripheral B output pin _1/
peripheral C output pin _0...

 
3. Setup Procedure Example 
 
3.  Setup Procedure Example 
This section explains a procedure example of setting up the I/O port. 
 Setup of the I/O Port 
By setting registers of the I/O port, select I/O direction and select GPIO/peripheral. 
Figure 3-1  shows a setup procedure example. 
Figure 3-1 Setup Procedure Example of the I/O Port 
 
  
Set peripherals 
EPFR peripheral output enabled 
Note: Output follows fixed priority 
EPFR peripheral input enabled 
Special pin selected 
Ye s   Ye s
No  No
No...

 
4. Register List 
 
4. Register List 
This section provides the register list of the I/O port. 
Ta b l e  4 - 1 provides the register list. 
Table 4-1 Register List of the I/O Port 
Abbreviation Register name See 
PFR0  Port function setting register 0 
PFR1 Port function setting register 1 
PFR2 Port function setting register 2 
PFR3 Port function setting register 3 
PFR4 Port function setting register 4 
PFR5 Port function setting register 5 
PFR6 Port function setting register 6 
PFR7 Port function...

 
4. Register List 
 
Abbreviation Register name  See 
PDIR3 Port input data register 3 
PDIR4 Port input data register 4 
PDIR5 Port input data register 5 
PDIR6 Port input data register 6 
PDIR7 Port input data register 7 
PDIR8 Port input data register 8  4.4 
PDOR0 
Port output data register 0 
PDOR1 Port output data register 1 
PDOR2 Port output data register 2 
PDOR3 Port output data register 3 
PDOR4 Port output data register 4 
PDOR5 Port output data register 5 
PDOR6 Port output data register 6...

 
4. Register List 
 
4.1.  Port Function Setting Register (PFRx) 
The PFRx register selects usage of a pin. 
 List of PFR Register Configuration 
  31    16 15    0  Initial 
value  Attribute Support 
 reserved  PFR0 0x001FR/W P0F to P00 
 reserved  PFR1 0x0000 R/W P1F to P10 
 reserved  PFR2 0x0000 R/W P2F to P20 
 reserved  PFR3 0x0000 R/W P3F to P30 
 reserved  PFR4 0x0000 R/W P4F to P40 
 reserved  PFR5 0x0000 R/W P5F to P50 
 reserved  PFR6 0x0000 R/W P6F to P60 
 reserved  PFR7 0x0000 R/W P7F to...