Fujitsu Series 3 Manual

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   36 
 Description of Each State 
Disable state  
See the hardware transfer (EM=0)  procedure. 
Wait -1st -trigger  state  
See the hardware transfer (EM=0)  procedure. 
Transfer state  
In this state, the channel to be controlled has received the first transfer request from the Peripheral. A 
channel in this state performs transfer operation as specified.  In the case of EM=1 , it moves to 
Wa i t...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   37 
8. Wait -1st -trigger  state / Post -transfer process  
In the case of EM=1 , EB is not cleared upon the completion of the transfer. (DE=1, EB=1, DH=0000, 
PB=0)  is set and it moves to  Wa i t-1st -trigger  state. When the next transfer request is generated from the 
Peripheral, therefore, the next transfer starts without an instruction from CPU.  
If it mo ves to Wa i t-1st -trigger  state due...

    4. DMAC Control  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   38 
Additional Matter 1  
See Additional Matter 1 in the hardware transfer (EM=0)  procedure.  
Additional Matter  2 
See Additional Matter 2 in the hardware transfer (EM=0)  procedure.  
In the case of EM=1 , Additional Matter 2 does not apply, because EB is not cleared during the transfer 
operation.  
Additional Matter  3 
See Additional Matter 3 in the hardware transfer (EM=0)  procedure....

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   39 
5.  Registers of DMAC 
This chapter describes each register function of DMAC.  
 
5.1 List of Registers  
5.2  Entire  DMAC  Configuration Register (DMACR ) 
5.3  Configuration A  Register  (DMACA ) 
5.4  Configuration B Register  (DMACB ) 
5.5  Transfer Source Address  Register  (DMACSA ) 
5.6  Transfer Destination Address Register  (DMACDA ) 
5.7  Notes  on Register Setting  
 
CHAPTER  8:...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMA C 
FUJITSU SEMICONDUCTOR CONFIDENTIAL   40 
5.1.  List of Registers  
Table 5-1 shows a list of DMAC control registers. 
Table 5-1  List of DMAC Control Registers  
Abbreviation Ch. Controlled Register name See 
DMACR All Entire DMAC configuration register 5.2 
DMACA0 
ch.0 
Configuration A register 5.3 
DMACB0 Configuration B register 5.4 
DMACSA0 Transfer source address register 5.5 
DMACDA0 Transfer destination address register 5.6...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   41 
5.2.  Entire DMAC  Configuration Register  (DMACR ) 
This section describes  entire DMAC configuration re gister (DMACR).  
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field DE DS - PR DH[3:0] - - - - - - - - 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   42 
[bit29] Reserved  
 
[bit28] PR : Priority Rotation  This bi t controls the order of transfer priority among channels.  
When this bit is set to "0" , the priority order is fixed for all of the channels.  
When this bit is set to "1" , the priority order is determined in a rotation method for all of the channels.  
bit28 Function 
0 Fixes the priority order....

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   43 
5.3.  Configuration A Register  (DMACA ) 
This section describes  configuration A  register  (DMACA ). 
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field EB PB ST IS[5:0] - - - BC[3:0] 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field TC[15:0] 
Attribute R/W 
Initial 
Va l...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAP TER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   44 
This bit can be used to put a transfer on pause without resetting the configuration register of the relevant 
channel.  
bit30 Function 
0 Cancels the pause of the transfer of the relevant channel. 
1 Puts the transfer of the relevant channel on pause. 
 
[bit29] ST : Software Trigger  
This bit is used to generate a software transfer request  for an individual channel. 
When this bit is set...

    5. Registers of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   45 
bit28:23 Function 
110100 IDREQ[20] 
110101 IDREQ[21] 
110110 IDREQ[22] 
110111 IDREQ[23] 
111000 IDREQ[24] 
111001 IDREQ[25] 
111010 IDREQ[26] 
111011 IDREQ[27] 
111100 IDREQ[28] 
111101 IDREQ[29] 
111110 IDREQ[30] 
111111 IDREQ[31] 
Setting other 
than above  Setting prohibited
 
 
[bit22:20] :  Reserved 
 
[bit19:16] BC : Block Count  
These bits specify the number of blocks for...