Samsung Exynos 5 User Manual

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-8  
12.3.6.1 Infra-Red Mode 
The Exynos 5250 UART block supports both Infra-Red (IR) transmission and reception. It is selected by setting 
the Infra-red-mode bit in the UART line control register (ULCONn). Figure 12-4 illustrates how to implement the IR 
mode.  
In IR transmit mode, the transmit pulse comes out at the rate of 3/16, that is, normal serial transmit rate (when the 
transmit data bit is 0)....

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-9  
Figure 12-6 illustrates the Infra-Red Transmit Mode Frame Timing diagram. 
 
    Figure 12-6   Infra-Red Transmit Mode Frame Timing Diagram 
 
Figure 12-7 illustrates the Infra-Red Receive Mode Frame Timing diagram. 
 
    Figure 12-7   Infra-Red Receive Mode Frame Timing Diagram 
 0
Start
Bit
Stop
Bit
Data  Bit s
IR  Trans mit  Frame
Bit
TimePuls e W idth  = 3/16  Bit  Fram e
000011111 0
Start
Bit
Stop
Bit...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-10  
12.4 UART Input Clock  
Figure 12-8 illustrates the Input Clock diagram for UART. 
 
  
    Figure 12-8   Input Clock Diagram for UART 
Exynos 5250 provides UART with a variety of clocks. The UART uses SCLK_UART clock which is from clock 
controller. You can also select SCLK_UART from various clock sources. Refer to Chapter 7 Clock Controller for 
more information on SCLK_UART. 
 System Controller...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-11  
12.5 I/O Description 
Signal I/O Description Pad Type 
UART_0_RXD Input Receives data for UART0 XuRXD_0 muxed 
UART_0_TXD Output Transmits data for UART0 XuTXD_0 muxed 
UART_0_CTSn Input Clears to send (active low) for UART0 XuCTSn_0 muxed 
UART_0_RTSn Output Requests to send (active low) for UART0 XuRTSn_0 muxed 
UART_1_RXD Input Receives data for UART1 XGPIO_URXD_1 muxed 
UART_1_TXD Output Transmits data...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-12  
12.6 Register Description 
12.6.1 Register Map Summary  
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
Register Offset Description Reset Value 
ULCONn 0x0000 Specifies line control 0x0000_0000 
UCONn 0x0004 Specifies control 0x0000_3000 
UFCONn 0x0008 Specifies FIFO...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-13  
12.6.1.1 ULCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0=
Infrared=
mode=[6]=RW=
Determines=whether to use the Infrared...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-14  
12.6.1.2 UCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0=
Tx DMA=burst 
size=[22:20]=RW=
Tx DMA Burst Size=
Indicates the...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-15  
Name Bit Type Description Reset Value 
Rx Time-out 
DMA suspend 
enable 
[10] R/W 
Enables Rx DMA FSM to suspend when Rx Time-out occurs 
0 = Disables suspending Rx DMA FSM 
1 = Enables suspending Rx DMA FSM 
0 
Tx Interrupt 
Type [9] RW 
Interrupt request type(2) 
0 = Pulse (interrupt is requested when the Tx buffer is empty 
in the Non-FIFO mode, or when it reaches Tx FIFO Trigger 
Level in the FIFO mode)...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-16  
Name Bit Type Description Reset Value 
11 = Reserved 
NOTE:  
1. DIV_VAL = UBRDIVn + UFRACVAL/16. Refer to Section 12.6.1.11 UBRDIVn (n = 0 to 4) and 
 12.6.1.12 UFRACVALn (n = 0 to 4) for more information.  
2. Exynos 5250 uses a level-triggered interrupt controller. Therefore, these bits must be set to 1 for every transfer. 
3. When the UART does not reach the FIFO trigger level, and it does not receive...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-17  
12.6.1.3 UFCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0008, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0=
Tx=FIFO=
Trigger Level=x10:8]=RW=
Determines=the trigger level...