Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 11 Watchdog Timer 
 11-4  
11.4 Register Description 
11.4.1 Register Map Summary  
 Base Address: 0x101D_0000 
Register Offset Description Reset Value 
WTCON 0x0000 Watchdog timer control register 0x0000_8021 
WTDAT 0x0004 Watchdog timer data register 0x0000_8000 
WTCNT 0x0008 Watchdog timer count register 0x0000_8000 
WTCLRINT 0x000C Watchdog timer interrupt clear register Undefined 
 
 
  

Samsung Confidential  
Exynos 5250_UM 11 Watchdog Timer 
 11-5  
11.4.1.1 WTCON  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_8021 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved==0=
Prescaler value=[15:8]=RW=Prescaler value=
The valid range is=from 0 to (28-1). 0x80 
RSVD [7:6] –=
Reserved==
(These two bits must be set to 00 in normal=
operation.)=
00=
Watchdog timer=[5]=RW=
Enables or disables t atchdog timer bit=
0 = Disables WDT bit=
1 =...

Samsung Confidential  
Exynos 5250_UM 11 Watchdog Timer 
 11-6  
11.4.1.2 WTDAT  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x0004, Reset Value = 0x0000_8000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved==0=
Count reload value=[15:0]=RW=WDT count value for reload.=0x8000=
=
The WTDAT register=specifies=the time-out duration. You cannot load the content of WTDAT into the timer counter=
at initial=t DT=operation.=After the WDTs first time-out using 0x8000=(initial value),...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-1  
12 Universal Asynchronous Receiver and 
Transmitter 
12.1 Overview 
The Universal Asynchronous Receiver and Transmitter (UART) in Exynos 5250 provide:  
Four independent channels with asynchronous and serial input/output ports for general purpose (Channel 0 to 3), 
and One channel in ISP (ISP-UART Channel 0) 
All ports operate in an Interrupt-based or a DMA-based mode. The UART generates an interrupt or a...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-2  
12.2 Features 
 All channels support Interrupt-based operation 
 All channels, except ISP-UART Channel 0, support DMA-based or Interrupt-based operation 
 UART Channel 0 with 256-byte FIFO, Channel 1 and ISP-UART Channel 0 with 64-byte FIFO, Channel 2 and 
3 with 16-byte FIFO 
 All channels, except UART Channel 3, support Auto Flow Control with nRTS and nCTS 
 Supports Handshake Transmit/Receive...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-3  
12.3 UART Description 
This section describes UART operations, such as Data Transmission, Data Reception, Interrupt Generation, 
Baud-rate Generation, Loop-back mode, Infrared modes, and Auto Flow Control.  
 
12.3.1 Data Transmission 
The data frame for transmission is programmable. It consists of a start bit, five to eight data bits, an optional parity 
bit, and one to two stop bits, specified by the line...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-4  
12.3.3 Auto Flow Control (AFC) 
The UART0, 1 and 2 in Exynos 5250 support Auto Flow Control (AFC) using nRTS and nCTS signals. In this 
case, it can be connected to external UARTs. To connect UART to a Modem, disable the AFC bit in UMCONn 
register, and control the signal of nRTS using software.  
In AFC, the nRTS signal depends on the condition of the receiver, whereas the nCTS signal controls the operation...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-5  
12.3.4 Non Auto-Flow Control (Controlling nRTS and nCTS by Software) 
12.3.4.1 Rx Operation with FIFO 
This procedures describes the Rx Operation with FIFO: 
1. Select the transmit mode (Interrupt or DMA mode) 
2. Check the value of Rx FIFO count in UFSTATn register. When the value is less than 16, you must set the  
 value of UMCONn[0] to 1 (activate nRTS). However, when the value is equal to or greater...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-6  
12.3.5 Interrupt/DMA Request Generation 
Each UART in Exynos 5250 comprises of seven status (Tx/Rx/Error) signals: Overrun Error, Parity Error, Frame 
Error, Break, Receive Buffer Data Ready, Transmit Buffer Empty, and Transmit Shifter Empty. These conditions 
are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). 
The Overrun Error, Parity Error, Frame Error and Break Condition specify...

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-7  
12.3.6 UART Error Status FIFO 
UART contains the error status FIFO besides the Rx FIFO register. The Error Status FIFO indicates the date that 
is received with an error, among FIFO registers. An error interrupt is issued only when the data that contains error 
is ready to read out. To clear the error status FIFO, URXHn with an error and UERSTATn must be read out. 
For example, it is assumed that the UART Rx...