Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-17  
Name Bit  Type Description Reset Value 
inverter on/off 1 = TOUT_0 Inverter-On 
Timer 0 manual 
update [1] RW 0 = No Operation    
1 = Updates TCNTB0,TCMPB0 0x0 
Timer 0 start/stop [0] RW 0 = Stops     
1 = Starts Timer 0 0x0 
  

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-18  
10.5.1.4 TCNTB0  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x000C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 0 count 
buffer [31:0] RW Timer 0 Count Buffer register 0x0000_0000 
 
10.5.1.5 TCMPB0 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000 
Name...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-19  
10.5.1.7 TCNTB1  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0018, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 1 count 
buffer [31:0] RW Timer 1 Count Buffer register 0x0000_0000 
 
10.5.1.8 TCMPB1 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x001C, Reset Value = 0x0000_0000 
Name...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-20  
10.5.1.10 TCNTB2 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0024, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 2 count 
buffer [31:0] RW Timer 2 Count Buffer register 0x0000_0000 
 
10.5.1.11 TCMPB2 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0028, Reset Value = 0x0000_0000 
Name...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-21  
10.5.1.13 TCNTB3  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 3 count 
buffer [31:0] RW Timer 3 Count Buffer register 0x0000_0000 
 
10.5.1.14 TCMPB3 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0034, Reset Value = 0x0000_0000...

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-22  
10.5.1.16 TCNTB4  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x003C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 4 count 
buffer [31:0] RW Timer 4 Count Buffer register 0x0000_0000 
 
10.5.1.17 TCNTO4 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0040, Reset Value = 0x0000_0000...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-23  
10.5.1.18 TINT_CSTAT  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0044, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
RSVD [31:10] –=Reserved Bits=0x00000=
Timer 4 
interrupt status=[9]=p=Timer 4 Interrupt Status=bit==
Clears by writing 1 on this bit.=0x0=
Timer 3 
interrupt status=[8]=p=Timer 3 Interrupt Status=bit==
Clears by writing 1 on this...

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Exynos 5250_UM 11 Watchdog Timer 
 11-1  
11 Watchdog Timer 
11.1 Overview 
Watchdog Timer (WDT) in Exynos 5250 is a timing device. You can use this device to resume the controller 
operation after malfunctioning due to noise and system errors. You can use WDT as a normal 16-bit interval timer 
to request interrupt service. WDT generates the reset signal. 
Both of WDT and PWM timer are normal generate internal interrupts for the ARM subsystem. The difference 
between WDT and PWM...

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Exynos 5250_UM 11 Watchdog Timer 
 11-2  
11.3 Functional Description 
This section includes: 
 WDT Operation 
 WTDAT and WTCNT 
 WDT Start 
 Consideration of debugging environment 
  
11.3.1 WDT Operation 
WDT timer uses PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding WDT 
clock and it divides the resulting frequency again.  
Figure 11-1 illustrates the functional block diagram of the WDT. 
 
    Figure 11-1   Watchdog Timer Block...

Samsung Confidential  
Exynos 5250_UM 11 Watchdog Timer 
 11-3  
11.3.2 WTDAT and WTCNT 
After you enable the WDT, you cannot reload the value of the Watchdog Timer Data (WTDAT) register 
automatically into the Watchdog Timer Counter (WTCNT) register. Therefore, you must write an initial value to the 
WTCN register before WDT starts. . 
 
11.3.3 WDT Start 
To start WDT, set WTCON[0] and WTCON[5] as 1. 
 
11.3.4 Consideration of Debugging Environment 
WDT must not operate when the Exynos 5250 is in debug...