Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-43  
7.5.1.32 IMSR7 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x007C, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=–=
EINTx15]=[25]=o=Masked interrupt=pending status==
If the corresponding interrupt enable bit is=0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx14]=[24]=o=–=...

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-44  
7.5.1.33 CIPSR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0100, Reset Value = Undefined 
Name Bit Type Description Reset Value 
INTG31 [31] R 
Combined interrupt pending status  
0 = The combined interrupt is not pending. 
1 = The combined interrupt is pending. This 
indicates that the corresponding interrupt request 
to the GIC is asserted. 
–=
INTG30=x30]=o=–=
INTG29=x29]=o=–=...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-1  
8 DMA (Direct Memory Access) Controller 
8.1 Overview 
Exynos 5250 has three DMA controller: 
 Two DMA controller transfers from Memory to Memory. (MDMA0, MDMA1) 
 One DMA controller transfers Peripheral-to-Memory and vice-versa. (PDMA) 
The MDMA Controller consists of one DMA330 and a few logics. The PDMA Controller consists of two DMA330 
(PDMA0 and PDMA1) and dma_mapper. 
Figure 8-1 illustrates the two type of DMA...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-2  
8.2 Features 
Features of DMA Controller are: 
Features MDMA PDMA 
Supports data size Up to double word (64-bit) Up to word (32-bit) 
Supports burst size Up to 16 burst Up to 8 burst 
Supports channel 8 channels at the same time 16 channels at the same time 
 
Refer these features for DMA and for writing DMA assembly code. 
NOTE: DMA Controller sends only one interrupt to Interrupt Controller for each DMA although each...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-3  
Module No.  Module No.  Module No.  
10 I2S0_TX 10 I2S0_TX 10 – 
9 I2S0_RX 9 I2S0_RX 9 – 
8 I2S0S_TX 8 I2S0S_TX 8 – 
7 SPI2_TX 7 SPDIF 7 – 
6 SPI2_RX 6 PW M 6 – 
5 SPI0_TX 5 SPI1_TX 5 – 
4 SPI0_RX 4 SPI1_RX 4 – 
3 PCM2_TX 3 PCM1_TX 3 – 
2 PCM2_RX 2 PCM1_RX 2 – 
1 PCM0_TX 1 PCM0_TX 1 – 
0 PCM0_RX 0 PCM0_RX 0 – 
 
Ensure to verify the CLKGATE status when PDMA0 or PDMA1 are enabled. 
 
  

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-4  
8.3 Functional Description 
8.3.1 Instruction 
Please refer to the PL330 TRM, AMBA DMA Controller DMA-330 technical reference manual revision r1p1 from 
ARM®.  
 
8.3.1.1 Security Scheme 
MDMA controller and PDMA controller run in the non-secure mode only. 
 
8.3.1.2 Summary 
 Configuring DMAC: 
You can configure DMAC with up to eight DMA channels. Each channel is capable of supporting a single 
concurrent thread of...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-5  
8.4 Register Description 
Most Special Function Registers (SFRs) are read-only. The main role of SFR is to verify the DMA330 status. 
There are many SFRs for DMA330. In this section describes Exynos 5250-specific SFRs only. Please refer to the 
PL330 TRM, AMBA DMA Controller DMA-330 technical reference manual revision r1p1 from ARM®  for more 
information. 
 
8.4.1 Register Map Summary 
 Base Address: 0x1080_0000...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-6  
Register Offset Description Reset Value 
CS5 0x0128 Specifies the channel status for DMA channel 5. 0x0 
CS6 0x0130 Specifies the channel status for DMA channel 6. 0x0 
CS7 0x0138 Specifies the channel status for DMA channel 7. 0x0 
CPC0 0x0104 Specifies the channel PC for DMA channel 0. 0x0 
CPC1 0x010C Specifies the channel PC for DMA channel 1. 0x0 
CPC2 0x0114 Specifies the channel PC for DMA channel 2. 0x0 
CPC3...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-7  
Register Offset Description Reset Value 
LC0_0 0x040C Specifies the loop counter 0 for DMA channel 0. 0x0 
LC0_1 0x042C Specifies the loop counter 0 for DMA channel 1. 0x0 
LC0_2 0x044C Specifies the loop counter 0 for DMA channel 2. 0x0 
LC0_3 0x046C Specifies the loop counter 0 for DMA channel 3. 0x0 
LC0_4 0x048C Specifies the loop counter 0 for DMA channel 4. 0x0 
LC0_5 0x04AC Specifies the loop counter 0 for DMA...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-8  
Register Offset Description Reset Value 
CR3 0x0E0C Specifies the configuration register 3. 0xFFFF_FFFF 
CR4 0x0E10 Specifies the configuration register 4.  0x0000_0001 
CRDn 0x0E14 Specifies the configuration register Dn. 0x03F7_3733 
RSVD 0x0E18 
to 0x0E7C Reserved Undefined 
WD 0x0E80 Watchdog register. 0x0 
periph_id_n 0x0FE0 
to 0x0FEC Specifies the peripheral Identification registers 0-3. Configuration-
dependent...