Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-11  
SPI Port No Id Int_e_combiner Interrupt Source Source Block 
IntG2_1 SYSMMU_GSCL0[1] – 
IntG2_0 SYSMMU_GSCL0[0] – 
1 33 
IntG1_7 CPU_nCNTVIRQ[0] – 
IntG1_6 CPU_nCNTPSIRQ[0] – 
IntG1_5 CPU_nCNTPSNIRQ[0] – 
IntG1_4 CPU_nCNTHPIRQ[0] – 
IntG1_3 CPU_nCTIIRQ[0] – 
IntG1_2 CPU_nPMUIRQ[0] – 
IntG1_1 CPU_PARITYFAILSCU[0] – 
IntG1_0 CPU_PARITYFAIL0 – 
0 32 
IntG0_7 TZASC_XR1BXW – 
IntG0_6 TZASC_XR1BXR – 
IntG0_5 TZASC_XLBXW – 
IntG0_4...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-12  
Table 6-4   External GIC Interrupt Table (PPI[15:0]) 
PPI Port No ID Interrupt Source Source Block 
15 31 – – 
14 30 nCNTPNSIRQ CPU 
13 29 nCNTPSIRQ CPU 
12 28 – – 
11 27 nCNTVIRQ CPU 
10 26 nCNTHPIRQ CPU 
9 25 Virtual maintenance interrupt GIC 
8 24 – – 
7 23 – – 
6 22 – – 
5 21 – – 
4 20 – – 
3 19 – – 
2 18 – – 
1 17 – – 
0 16 – – 
 
  

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-13  
6.3 Register Description 
6.3.1 Register Map Summary 
 Base_Address_D = 0x1048_1000 
Register Offset Description Reset Value 
Distributor Register Map 
GICD_CTLR 0x0000 Distributor control register 0x0000_0000 
GICD_TYPER 0x0004 Interrupt controller type register 0x0000_FC24 
GICD_IIDR 0x0008 Distributor implementer identification register 0x0200_043B 
GICD_IGROUPR0 0x0080 Interrupt security registers (SGI, PPI) 0x0000_0000...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-14  
Register Offset Description Reset Value 
GICD_ISACTIVER4 0x0310 Interrupt set-active registers (SPI[127:96]) 0x0000_0000 
GICD_ICACTIVER0 0x0380 Interrupt clear-active registers (SGI, PPI) 0x0000_0000 
GICD_ICACTIVER1 0x0384 Interrupt clear-active registers (SPI[31:0]) 0x0000_0000 
GICD_ICACTIVER2 0x0388 Interrupt clear-active registers (SPI[63:32]) 0x0000_0000 
GICD_ICACTIVER3 0x038C Interrupt clear-active registers (SPI[95:64])...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-15  
Register Offset Description Reset Value 
GICD_IPRIORITYR31 0x047C Priority level register (SPI[95:92]) 0x0000_0000 
GICD_IPRIORITYR32 0x0480 Priority level register (SPI[99:96]) 0x0000_0000 
GICD_IPRIORITYR33 0x0484 Priority level register (SPI[103:100]) 0x0000_0000 
GICD_IPRIORITYR34 0x0488 Priority level register (SPI[107:104]) 0x0000_0000 
GICD_IPRIORITYR35 0x048C Priority level register (SPI[111:108]) 0x0000_0000 
GICD_IPRIORITYR36...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-16  
Register Offset Description Reset Value 
GICD_ITARGETSR28 0x0870 Processor targets register (SPI[83:80]) 0x0000_0000 
GICD_ITARGETSR29 0x0874 Processor targets register (SPI[87:84]) 0x0000_0000 
GICD_ITARGETSR30 0x0878 Processor targets register (SPI[91:98]) 0x0000_0000 
GICD_ITARGETSR31 0x087C Processor targets register (SPI[95:92]) 0x0000_0000 
GICD_ITARGETSR32 0x0880 Processor targets register (SPI[99:96]) 0x0000_0000...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-17  
Register Offset Description Reset Value 
GICD_PIDR5 0x0FD4 Peripheral ID 5 register 0x0000_0000 
GICD_PIDR6 0x0FD8 Peripheral ID 6 register 0x0000_0000 
GICD_PIDR7 0x0FDC Peripheral ID 7 register 0x0000_0000 
GICD_PIDR0 0x0FE0 Peripheral ID 0 register 0x0000_0090 
GICD_PIDR1 0x0FE4 Peripheral ID 1 register 0x0000_00B4 
GICD_PIDR2 0x0FE8 Peripheral ID 2 register 0x0000_002B 
GICD_PIDR3 0x0FEC Peripheral ID 3 register 0x0000_0000...

Samsung Confidential  
Exynos 5250_UM 6 Interrupt Controller 
 6-18  
 Base_Address_V = 0x1048_4000 
Register Offset Description Reset Value 
Virtual Interface Control Register Map 
GICH_HCR 0x0000 Hypervisor control register 0x0000_0000 
GICH_VTR 0x0004 VGIC type register 0x9000_0003 
GICH_VMCR 0x0008 Virtual machine control register 0x004C_0000 
GICH_MISR 0x0010 Maintenance interrupt status register 0x0000_0000 
GICH_EISR0 0x0020 End of interrupt status register 0x0000_0000 
GICH_ELSR0 0x0030 Empty...

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-1  
7 Interrupt Combiner 
7.1 Overview 
The interrupt controller subsystem in Exynos 5250 consists of generic interrupt controllers and interrupt 
combiners. Some interrupt sources are grouped in Exynos 5250. The interrupt combiner combines several 
interrupt sources as a group. Several interrupt requests in a group, create a group interrupt request, which 
produces a single request signal. Therefore, the interrupt input sources of the...

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-2  
7.3 Interrupt Sources 
Table 7-1 lists the interrupt groups of interrupt combiner. 
Table 7-1   Interrupt Groups of Interrupt Combiner 
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG0 TZASC 
[7] TZASC_XR1BXW 
SYSMEM 
[6] TZASC_XR1BXR 
[5] TZASC_XLBXW 
[4] TZASC_XLBXR 
[3] TZASC_DRBXW 
[2] TZASC_DRBXR 
[1] TZASC_CBXW 
[0] TZASC_CBXR 
INTG1 PARITYFAIL0/CPUCTI0/PMU0 
[7] CPU_nCNTVIRQ[0] 
CPU0 
[6]...