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Samsung Exynos 5 User Manual

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Page 591

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-13  
7.5.1.4 IMSR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x000C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] R 
Masked interrupt pending status  
If the corresponding interrupt enable bit is set to 
0, the IMSR bit is read out as 0. 
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_SCALEoPISP[0]=[30]=o=–=...

Page 592

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-14  
7.5.1.5 IESR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt...

Page 593

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-15  
7.5.1.6 IECR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0014, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is=cleared, the=
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable...

Page 594

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-16  
7.5.1.7 ISTR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0018, Reset Value = Undefined 
Name Bit Type Description Reset Value 
RSVD [31] –=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=o=–=
SYSMMU_TV_M0x0]=[28]=o=–=...

Page 595

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-17  
7.5.1.8 IMSR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x001C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
RSVD [31] –=
Masked interrupt pending status =
If=the corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=o=–=...

Page 596

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-18  
7.5.1.9 IESR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current...

Page 597

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-19  
7.5.1.10 IECR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0024, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] RW Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked. 
Write 
0 = Does not change the current setting 
1 = Clear the interrupt enable bit to 0 
Read 
The current...

Page 598

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-20  
7.5.1.11 ISTR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0028, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] R 
Interrupt pending status  
The corresponding interrupt enable bit does not 
affect this pending status.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_DRCISP[0]=[30]=o=–=
oSVa=[29]=–=–=
oSVa=[28]=–=–=...

Page 599

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-21  
7.5.1.12 IMSR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x002C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] R 
Masked interrupt pending status  
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_DRCISP[0]=[30]=o=–=
oSVa=[29]=–=–=...

Page 600

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-22  
7.5.1.13 IESR3 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt...

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