Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-9  
 Base Address: 0x121A_0000 (PDMA0) 
 Base Address: 0x121B_0000 (PDMA1) 
Register Offset Description Reset Value 
PDMA0/PDMA1 
DSR 0x0000 Specifies the DMA status register. 0x0000_0200 
DPC 0x0004 Specifies the DMA program counter register. 0x0 
RSVD 0x0008 
to 0x001C Reserved Undefined 
INTEN 0x0020 Specifies the interrupt enable register. 0x0 
INT_EVENT 
_RIS 0x0024 Specifies the event status register.  0x0 
INTMIS...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-10  
Register Offset Description Reset Value 
CPC3 0x011C Specifies the channel PC for DMA channel 3. 0x0 
CPC4 0x0124 Specifies the channel PC for DMA channel 4. 0x0 
CPC5 0x012C Specifies the channel PC for DMA channel 5. 0x0 
CPC6 0x0134 Specifies the channel PC for DMA channel 6. 0x0 
CPC7 0x013C Specifies the channel PC for DMA channel 7. 0x0 
RSVD 0x0140 
to 0x03FC Reserved Undefined 
SAR_0 0x0400 Specifies the source...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-11  
Register Offset Description Reset Value 
LC0_6 0x04CC Specifies the loop counter 0 for DMA channel 6. 0x0 
LC0_7 0x04EC Specifies the loop counter 0 for DMA channel 7. 0x0 
LC1_0 0x0410 Specifies the loop counter 1 for DMA channel 0. 0x0 
LC1_1 0x0430 Specifies the loop counter 1 for DMA channel 1. 0x0 
LC1_2 0x0450 Specifies the loop counter 1 for DMA channel 2. 0x0 
LC1_3 0x0470 Specifies the loop counter 1 for DMA...

Samsung Confidential  
Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-12  
Register Offset Description Reset Value 
periph_id_n 0x0FE0 
to 0x0FEC Specifies the peripheral identification registers 0-3.  Configuration-
dependent 
pcell_id_n 0x0FF0 
to 0x0FFC Specifies the prime cell identification registers 0-3. Configuration-
dependent 
NOTE: The SFR provides description for only the restricted and fixed part of some SFR. DMA330 TRM provides detailed 
information of other parts and other SFRs....

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-1  
9 SROM Controller 
9.1 Overview 
Exynos 5250 SROM Controller (SROMC) support external 8/16-bit NOR Flash/PROM/SRAM memory. 
Exynos 5250 SROM Controller supports 4-bank memory up to maximum 128 Kbyte per bank. 
 
9.2 Features 
 Supports SRAM, various ROMs and NOR flash memory 
 Supports only 8 or 16-bit data bus 
 Address space: Up to 128 KB per Bank 
 Supports 4 banks. 
 Fixed memory bank start address 
 External wait to extend the bus...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-2  
9.4 Functional Description 
SROM Controller supports SROM interface for Bank0 to Bank3.  
 
9.4.1 nWAIT Pin Operation 
If the W AIT signal corresponding to each memory bank is enabled, the external nWAIT pin should prolong the 
duration of nOE while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the 
next clock after sampling nWAIT is high. The nW E signal has the same relation with nOE signal....

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-3  
9.4.2 Programmable Access Cycle 
 
    Figure 9-3   SROM Controller Read Timing Diagram 
SROM controller supports page read operations for 32-bit 1 word. Figure 9-3 shows an example timing diagram of 
16-bit data page read operation. Figure 9-4 shows an example timing diagram of 8-bit data page read operation. 
 
  
    Figure 9-4   SROM Controller Page Read Timing Diagram HCLK
ADDR
nGCS
DATA(R)
Tacs
Tacc
ADDRESS 0
DATA 0
nOETcos
Tacp
DATA...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-4  
 
    Figure 9-5   SROM Controller Write Timing Diagram 
 HCLK
ADDR
nGCS
DATA(W)
Tacs
Tacc
Tcoh
Tcah
ADDRESS
nW ETcos
DATA
Tacs=2-cycleTacp=don’tcareTcos=2-cycleTcoh=2-cycleTacc=3-cycleTcah=2-cycle  

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-5  
9.5 I/O Description 
Signal I/O Description Pad Type 
nGCS[3:0] Output Bank selection signal XsramCSn[3:0] muxed 
ADDR[15:0] Output SROM address bus  XsramADDR[15:0] muxed 
nOE Output SROM output enable XsramOEn muxed 
nW E Output SROM write enable XsramWEn muxed 
nW BE/nBE[1:0] Output SROM byte write enable/byte enable XsramBEn[1:0] muxed 
DATA[15:0] In/Out SROM data bus XsramDATA[15:0] muxed 
nW AIT Input SROM wait input XsramWAITn muxed...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-6  
9.6 Register Description 
9.6.1 Register Map Summary 
 Base Address: 0x1225_0000 
Register Offset Description Reset Value 
SROM_BW 0x0000 Specifies the SROM bus width & wait control 0x0000_0009 
SROM_BC0 0x0004 Specifies the SROM bank 0 control register 0x000F_0000 
SROM_BC1 0x0008 Specifies the SROM bank 1 control register 0x000F_0000 
SROM_BC2 0x000C Specifies the SROM bank 2 control register 0x000F_0000 
SROM_BC3 0x0010 Specifies the...